8-Bit Synchronous
Binary Up Counter
HIGH-PER.ORMANCE PRODUCTS
Description
The SK10/100E016 is a high-speed synchronous,
presettable, cascadable 8-bit binary counter.
The counter features internal feedback of TC*, gated by
the TCLD (terminal count load) pin. When TCLD is LOW
(or left open, in which case it is pulled LOW by the internal
pull-downs), the TC* feedback is disabled, and counting
proceeds continuously, with TC* going LOW to indicate
an all-one state. When TCLD is HIGH, the TC* feedback
causes the counter to automatically reload upon TC* =
LOW, thus functioning as a programmable counter. The
Qn outputs do not need to be terminated for the count
function to operate properly. To minimize noise and
power, unused Q outputs should be left unterminated.
SK10/100E016
.eatures
•
•
•
•
•
•
•
•
•
•
•
700 MHz Min Count Frequency
1000 ps CLK to Q, TC*
Internal TC* Feedback (Gated)
8-Bit
Fully Synchronous Counting and TC* Generation
Asynchronous Master Reset
Internal 75 kΩ Input Pulldown Resistors
Extended 100E V
EE
Range of –4.2V to –5.46V
Fully Compatible with MC10/100E016
Available in 28-Pin PLCC Package
ESD Protection of >4000V
.unctional Block Diagram
8 Bit Binary Counter - Logic Counter
PE
Q0
Q1
Q7
TCLD
QOM
CE*
BIT 0
MASTER
QOM*
SLAVE
Q0*
CE*
BIT 1
CE*
Q0*
Q1*
Q2*
Q3*
Q4*
Q5*
Q6*
BIT 7
PO
P1
P7
MR
CLK
BITS 2-6
5
TC*
Note that this diagram is provided for understanding of logic operation only. It should not be used for propagation
delays as many gate functions are achieved internally without incurring a full gate delay.
Revision 1/.ebruary 13, 2001
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SK10/100E016
HIGH-PER.ORMANCE PRODUCTS
PIN Description
Pinout
V CCO
PE*
CE*
TC*
Function Table
P7
P6
P5
25
MR
CLK
TCLD
V EE
NC
P0
P1
26
27
28
24
23
22
21
20
19
18
17
16
Q7
Q6
V CC
Q5
V CCO
Q4
Q3
CE*
X
L
L
PE*
L
H
H
H
X
X
TCLD
X
L
H
X
X
X
MR
L
L
L
L
L
H
CLK
Z
Z
Z
Z
ZZ
X
.unction
Load Parallel (P
n
to Q
n
)
Continuous Count
Count; Load Parallel on TC* = LOW
Hold
Masters Respond,
Slaves Hold
Reset (Qn: = LOW,
TC*: = HIGH)
28 Lead PLCC
1
(Top View)
2
3
4
5
P2
H
X
X
15
14
13
12
6
P3
7
P4
8
V CCO
9
Q0
10
Q1
11
Q2
Pin Names
Pin
P0 - P7
Q0 - Q7
CE*
PE*
MR
CLK
TC*
TCLD
.unction
Parallel Data (Preset) Inputs
Data Outputs
Count Enable Control Input
Parallel Load Enable Control Input
Master Reset
Clock
Terminal Count Output
TC-Load Control Input
Revision 1/.ebruary 13, 2001
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SK10/100E016
HIGH-PER.ORMANCE PRODUCTS
Application Information
Function Table
.unct i on
Load
Count
PE *
L
H
H
H
H
Load
Ho l d
L o a d On
Ter minal
Count
L
H
H
H
H
H
H
H
H
Reset
X
CE *
X
L
L
L
L
X
H
H
L
L
L
L
L
L
X
MR
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
T CL D
X
L
L
L
L
X
X
X
H
H
H
H
H
H
X
CL K
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
X
P7- P4
H
X
X
X
H
H
X
X
H
H
H
H
H
H
X
P3
H
X
X
X
H
H
X
X
L
L
L
L
L
L
X
P2
H
X
X
X
H
H
X
X
H
H
H
H
H
H
X
P1
L
X
X
X
L
L
X
X
H
H
H
H
H
H
X
P0
L
X
X
X
L
L
X
X
L
L
L
L
L
L
X
Q7 - Q4
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
Q3
H
H
H
H
H
H
H
H
H
H
H
L
L
H
L
Q2
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
Q1
L
L
H
H
L
L
L
L
L
H
H
H
H
L
L
Q0
L
H
L
H
L
L
L
L
H
L
H
L
H
L
L
TC
H
H
H
L
H
H
H
H
H
H
L
H
H
H
G
Cascading Multiple E016 Devices
For applications which call for larger than 8-bit counters,
multiple E016s can be tied together to achieve very
wide bit width counters. The active low terminal count
(TC*) output and count enable input (CE*) greatly
facilitate the cascading of E016 devices. Two E016s
can be cascaded without the need for external gating;
however, for counters wider than 16 bits, external OR
gates are necessary for cascade implementations.
Figure 3 below illustrates the cascading of 4 E016s to
build a 32-bit high frequency counter. Note that the
E101 gates are used to OR the terminal count outputs
of the lower order E016s to control the counting
operation of the higher order bits. When the terminal
count of the preceding device (or devices) goes low
(the counter reaches an all 1s state), the more
significant E016 is set in its count mode and will count
one binary digit upon the next positive clock transition.
In addition, the preceding devices will also count one
bit, sending their terminal count outputs back to a high
state, disabling the count operation of the more
significant counters, and placing them back into hold
modes. Therefore, for an E016 in the chain to count,
Revision 1/.ebruary 13, 2001
all of the lower order terminal count outputs must
be in the low state. The bit width of the counter can
be increased or decreased by simply adding or
subtracting E016 devices from Figure 3 and
maintaining the logic pattern illustrated in the same
figure.
The maximum frequency of operation for the
cascaded counter chain is set by the propagation
delay of the TC* output, the necessary setup time
of the CE* input, and the propagation delay through
the OR gate controlling it (for 16-bit counters the
limitation is only the TC* propagation delay and the
CE* setup time). Figure 3 shows EL01 gates used
to control the count enable inputs; however, if the
frequency of operation is lower, a lower ECL OR gate
can be used. Using the worst case guarantees for
these parameters, the maximum count frequency
for a greater than 16-bit counter is 500 MHz, and
for a 16-bit counter is 625 MHz. Note that this
assumes the trace delay between the TC* outputs
and the CE* inputs are negligible. If this is not the
case, estimates of these delays need to be added
to the calculations.
3
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SK10/100E016
HIGH-PER.ORMANCE PRODUCTS
Application Information
(continued)
LOAD
CE*
PE*
CE*
PE*
CE*
PE*
CE*
E016
LSB
E016
E016
E016
MSB
CLK
TC*
CLK
TC*
EL01
CLK
TC*
EL01
CLK
CLOCK
Figure 3. 32-Bit Cascaded E016 Counter
P
rogrammable Divider
The E016 has been designed with a control pin which
makes it ideal for use as an 8-bit programmable divider.
The TCLD pin (load on terminal count) when asserted
reloads the data present at the parallel input pin (Pn’s)
upon reaching terminal count (an all 1s state on the
outputs). Because this feedback is built internal to the
chip, the programmable division operation will run at very
nearly the same frequency as the maximum counting
frequency of the device. Figure 4 below illustrates the
input conditions necessary for utilizing the E016 as a
programmable divider set up to divide by 113.
H
L
L
L
H
H
H
H
Pn’s = 256 – 113 = 8F
16
= 1000 1111
where:
PO = LSB and P7 = MSB
Forcing this input condition as per the setup in Figure
4 will result in the waveforms of Figure 5. Note that
the TC* output is used as the divide output and the
pulse duration is equal to a full clock period. For
even divide ratios, twice the desired divide ratio can
be loaded into the E016, and the TC* output can
feed the clock input of a toggle flip-flop to create a
signal divided as desired with a 50% duty cycle.
Di v i d e
Ra t i o
2
3
P7
H
L
H
PE*
CE*
TCLD
CLK
P6
P5
P4
P3
P2
P1
P0
Preset Data Inputs
P7
H
H
H
H
l
l
H
H
H
l
l
L
L
L
P6
H
H
H
H
l
l
L
L
L
l
l
L
L
L
P5
H
H
H
H
l
l
L
L
L
l
l
L
L
L
P4
H
H
H
H
l
l
H
L
L
l
l
L
L
L
P3
H
H
H
H
l
l
L
H
H
l
l
L
L
L
P2
H
H
H
L
l
l
L
H
H
l
l
L
L
L
P1
H
L
L
H
l
l
L
H
H
l
l
H
L
L
P0
L
H
L
H
l
l
L
H
L
l
l
L
H
L
TC*
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
4
5
l
Figure 4. Mod 2 to 256 Programmable Divider
l
112
To determine what value to load into the device to
accomplish the desired division, the designer simply
subtracts the binary equivalent of the desired divide ratio
from the binary value for 256. As an example for a divide
ratio of 113:
113
114
l
l
254
255
256
Revision 1/.ebruary 13, 2001
4
®
®
®
®
P0
P7
P0
P7
P0
P7
P0
®
®
®
®
Q0
Q7
Q0
Q7
Q0
Q7
Q0
Q7
PE*
TC*
P7
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SK10/100E016
HIGH-PER.ORMANCE PRODUCTS
Application Information
(continued)
A single E016 can be used to divide by any ratio from 2
to 256 inclusive. If divide ratios of greater than 256
are needed, multiple E016s can be cascaded in a
manner similar to that already discussed. When E016s
are cascaded to build larger dividers, the TCLD pin will
no longer provide a means for loading on terminal count.
Because one does not want to reload the counters until
all of the devices in the chain have reached terminal
count, external gating of the TC* pins must be used for
multiple E016 divider chains.
Figure 6 shows a typical block diagram of a 32-bit divider
chain. Once again, to maximize the frequency of
operation, EL01 OR gates were used. For lower
frequency applications, a slower OR gate could replace
the EL01. Note that for a 16-bit divider, the OR function
feeding the PE* (program enable) input CANNOT be
placed by a wire OR tie as the TC* output of the least
significant E016 must also feed the CE* input of the
most significant E016. If the two TC* outputs were OR
tied, the cascaded count operation would not operate
properly. Because, in the cascaded form, the PE*
feedback is external and requires external gating, the
maximum frequency of operation will be significantly less
than the same operation in a single device.
Maximizing E016 Count Frequency
The E016 device produces 9 fast transitioning single-
ended outputs, thus VCC noise can become significant
in situations where all of the outputs switch
simultaneously in the same direction. This VCC noise
can negatively impact the maximum frequency of
operation of the device. Since the device does not
need to have the Q outputs terminated to count properly,
it is recommended that if the outputs are not going to
be used in the rest of the system, they should be
terminated. Not terminating the unused outputs will
not only cut down the VCC noise generated, but will
also save in total system power dissipation. Following
these guidelines will allow designers to either be more
aggressive in their designs or provide them with an
extra margin to the published databook specifications.
LOAD
CLOCK
1001 0000
1001 0001
1111 1100
1111 1101
1111 1110
1111 1111
LOAD
PE*
TC*
DIVIDE BY 113
Figure 5. Divide by 113 E016 Programmable Divider Waveforms
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