Can implement stepping motor drive systems simply by providing a DC power supply and a clock pulse generator.
<Control Block Features>
•
One of five drive types can be selected with the drive mode settings (M1, M2, and M3)
1) 2 phase excitation drive
2) 1-2 phase excitation drive
3) W1-2 phase excitation drive
4) 2W1-2 phase excitation drive
5) 4W1-2 phase excitation drive
•
Provides four freely selectable modes for the vector locus during microstepping drive: circular mode, one inside mode,
and two outside modes.
•
Phase retention even if excitation is switched.
•
The excitation phase state can be verified in real time using the MO1, MO2, and MOI signal output pins.
•
The CLK input counter block can be selected to be one of the following by the high/low setting of the M3 input pin.
1) Rising edge only
2) Both rising and falling edges
•
The CLK and RETURN input pins include built-in malfunction prevention circuits for external pulse noise.
•
ENABLE and RESET pins provided. These are Schmitt trigger inputs with built-in 20kΩ (typical) pull-up resistors.
•
No noise generation due to the difference between the A and B phase time constants during motor hold since external
excitation is used.
•
Microstepping operation supported even for small motor currents, since the reference voltage Vref can be set to any
value between 0V and 1/2VCC2.
<Driver Block>
•
External excitation PWM drive allows a wide operating supply voltage range (VCC1 = 10 to 45V) to be used.
•
Current detection resistor (0.33Ω) built-in the hybrid IC itself.
•
Power MOSFETs adopted for low drive loss.
•
Provides a motor output drive current of IOH = 1.5A.
Specifications
Absolute Maximum Ratings
at Ta = 25°C
Parameter
Maximum supply voltage 1
Maximum supply voltage 2
Input voltage
Output current
Repeated avalanche capacity
Allowable power dissipation
Operating substrate temperature
Junction temperature
Storage temperature
Symbol
VCC1 max
VCC2 max
VIN max
IOH max
Ear max
Pd max
Tc max
Tj max
Tstg
θc-a
= 0
No signal
No signal
Logic input pins
0.5s, 1 pulse, when VCC1 applied.
Load: R = 5Ω, L = 10mH for each phase.
Conditions
Ratings
52
-0.3 to +7.0
-0.3 to +7.0
2.2
38
12
105
150
-40 to +125
Unit
V
V
V
A
mJ
W
°C
°C
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Allowable Operating Ranges
at Ta = 25°C
Parameter
Supply voltage 1
Supply voltage 2
Input voltage
Phase driver withstand voltage
Output current
Symbol
VCC1
VCC2
VIH
VDSS
IOH
Tr1, 2, 3, and 4 (the A, A, B, and B outputs)
Duty 50%
With signals applied
With signals applied
Conditions
Ratings
10 to 45
5 ± 5%
0 to VCC2
100 (min)
1.5
Unit
V
V
V
V
A
No. 5227-2/19
STK672-040-E
Electrical Characteristics
at Tc = 25°C, VCC1 = 24V, VCC2 = 5V
Parameters
Control supply current
Output saturation voltage
Average output current
FET diode forward voltage
[Control Inputs]
Input voltage
VIH
VIL
IIH
IIL
Except for the Vref pin
Except for the Vref pin
Except for the Vref pin
Except for the Vref pin
0
125
1
250
4
1
10
510
V
V
μA
μA
Symbols
ICC
Vsat
Ioave
Vdf
Conditions
min
Pin 7, with ENABLE pin held low.
RL = 15Ω (I
≈
1.5 A)
Load: R = 3.5Ω / L = 3.8mH
For each phase, Vref
≈
1V
If = 1A
0.465
Rating
typ
4.5
1.4
0.517
1.2
max
15
1.9
0.569
1.8
mA
V
A
V
unit
Input current
[Vref Input Pin]
Input voltage
Input current
[Control Outputs]
Output voltage
[Current Distribution Ratio (A·B)]
2W1-2, W1-2, 1-2
2W1-2, W1-2
2W1-2
2W1-2, W1-2, 1-2
2W1-2
2W1-2, W1-2
2W1-2
2
PWM frequency
VI
II
Pin 8
Pin 8
0
1
2.5
V
μA
VOH
VOL
I = –3mA, pins MOI, MO1, MO2
I = +3mA, pins MOI, MO1, MO2
2.4
0.4
V
V
Vref
Vref
Vref
Vref
Vref
Vref
Vref
Vref
fc
θ
= 1/8
θ
= 2/8
θ
= 3/8
θ
= 4/8
θ
= 5/8
θ
= 6/8
θ
= 7/8
100
92
83
71
55
40
20
100
37
47
57
%
%
%
%
%
%
%
%
kHz
Note: A constant-voltage power supply must be used.
The design target value is shown for the current distribution ratio.
Package Dimensions
unit:mm (typ)
4161
53.0
9.0
22.0
1
2.0
21 2=42
22
4.0
1.0
0.5
0.4
2.9
No. 5227-3/19
VCC2
7
12
13
8
6
5
2
1
M4
M5
Vref
A
A
B
B
M1
+
–
Internal Block Diagram
9
Current
distribution
ratio switching
+
M2 10
Excitation mode
control
CWB 15
Phase
advance
counter
CLK 14
–
+
–
Rise/fall
detection and switching
Pseudo-sine
wave
generator
M3 11
RETURN 17
Rise detection
RESET 16
MOI 19
Phase excitation drive
signal generation
MO1 20
–
Excitation state monitor
STK672-040-E
MO2 21
+
ENABLE 18
RC oscillator
SG 22
SUB
4
+
–
Reference clock
generation
PWM control
3
PG
ITF02366
No. 5227-4/19
STK672-040-E
Test Circuit Diagrams
Vsat
VCC2
7
15Ω
Vdf
VCC1
7
Start
14
6
5
A
A
B
B
6
5
2
1
STK672-040-E
A
A
B
B
9
10
STK672-040-E
Vref=2.5V
VCC2
8
2
1
V
4
+
16
22
ITF02367
V
4
3
22
ITF02368
3
A
IIH, IIL
VCC2
Ioave, ICC, fc
VCC2
A
M1
M2
M3
M4
M5
7
9
10
11
12
13
14
STK672-040-E
15
16
17
18
8
22
VCC1
Start
14
9
10
7
6
2
5
1
A
A
B
B
a
b a
SW1
b
IIH
A
IIL
SW2
CLK
CWB
RESET
RETURN
ENABLE
Vref
Vref=1V
5V
Low when
measuring ICC
0V
0V
VCC2
8
STK672-040-E
18
VCC1
+
16
22
A
ITF02369
ITF02370
When measuring Ioave: With SW1 set to ‘a’, Vref = 1V
