Preliminary Information
SL1914
SL1914
Satellite Tuner Front End LNA with AGC
Preliminary Information
DS5137
ISSUE 1.6
April 1999
Features
q
q
q
q
q
q
Single chip solution for satellite tuner LNA and
AGC
Provides for 30 dB minimum AGC
Low DSB NF at maximum gain
High signal handling at minimum gain
Provides differential output drive
ESD protection (Normal ESD handling
procedures should be observed)
Ordering Information
SL1914A/KG/MP1S
SL1914A/KG/MP1T
Description
The SL1914 is a wideband LNA with AGC designed
primarily for application in satellite tuner front ends,
offering high signal handling capability with low noise
figure compatible with most common tuner input
requirements.
The SL1914 is optimised to complement the SL1925,
ZIF quadrature downconverter, integrating all the active
RF circuitry within the tuner, in a highly compact, efficient
solution, and offering a full 1-45 MS/s tuner capability.
Applications
q
q
q
Satellite receiver systems
Data communications systems
Master Antennae Distribution Systems
6
RF INPUT
2
5
OUTPUT
OUTPUTB
AGC
4
1
8
3
Vcca
Vccb
Vee
Figure 1 Block Diagram
1
SP1914
Preliminary Information
Vcca
RFIP
Vccb
N/C
8
SPOT
REF.
Vee
AGC
OP
OPB
MP8
Figure 2 Pin Connections
Quick Reference Data
Characteristic
Operating frequency
Input DSB NF at max gain
Maximum conversion gain
Minimum conversion gain
IPIP3
2T
IPIP2
2T
Table 1
950 - 2150
9
20
-10
117
127
Units
MHz
dB
dB
dB
dBµV
dBµV
Functional Description
The SL1914 is a bipolar, low noise AGC amplifier
designed primarily for application in satellite tuner front
ends. It contains a low noise input amplifier, an AGC
stage with a minimum of 30dB of gain control and a 75
Ohm output drive. It replaces all active circuitry in
conventional architectures.
The typical key performance numbers under nominal
load ambient and supply conditions are contained in
table headed Quick Reference Data.
2
Preliminary Information
Electrical Characteristics
SL1914
o
o
Tamb= -20 C to +70 C, Vee = 0V, Vcc = 5V±5%, These characteristics are guaranteed by either production test
or design. They apply within the specified ambient temperature and supply voltage unless otherwise stated.
Characteristic
Pin
Min
Value
Typ
110
950
75
8
9
11
-1
Max
150
2150
Units
Conditions
Supply current
Operating range
Input impedance
IF input return loss
Input DSB NF
Variation in NF with gain
setting
Conversion gain
minimum
maximum
Gain variation within
channel
Input referred 1 dB gain
compression
Input referred IP3
Input referred IP2
Variation in second and
third order intermodulation
intercept points with gain
setting
AGC control slope
variation
AGC control input current
Output impedance
Output return loss
1, 8
2
2
2
mA
MHz
Ω
dB
dB
dB/dB
AGC = 4V
Maximum gain, AGC = 0.75V
-10
21
+0.5
dB
dB
dB
dB
Differential power gain into 75Ω
Vagc = 4V
See note 1.
Vagc = 0.75V
AGC monotonic from Vee to Vcc
Maximum channel bandwidth of
54MHz, within range 950 -
2150MHz
Minimum specified gain setting
Minimum specified gain setting,
two tones at 99dBµV
Minimum specified gain setting,
two tones at 99dBµV
2
2
2
107
117
125
-1
dBµV
dBµV
dBµV
dB/dB
4
4
5, 6
5, 6
4:1
±350
75
6
µA
Ω
dB
Note 1: The AGC voltage should not exceed 4V.
3
SP1914
Preliminary Information
Absolute Maximum Ratings
All voltages referred to Vee at 0V.
Characteristics
Supply voltage
IFIN and IFINB input voltage
All I/O port DC offset
AGC input DC offset
Storage temperature
Junction temperature
Package thermal resistance,
chip to case
Package thermal resistance,
chip to ambient
Power consumption at 5.25V
ESD protection
2
Min
-0.3
-0.3
-0.3
-55
Max
7
117
VCC+0.3
4
150
150
39.8
120
790
Unit
V
dBµV
V
V
°C
°C
°C/W
°C/W
mW
kV
Mil std-883 latest revision
method 3015 class 1
Conditions
Transient condition only
Except AGC (pin 4)
Marker
1
2
3
4
Freq (MHz)
950
1250
1550
2150
Z real
Ω
77
80
44
29
Z imag
Ω
-6
-34
-44
-35
+j1
+j0.5
+j2
+j0.2
+j5
0
0.2
0.5
1
∆
2
∆
1
∆
2
5
X
3
∆
4
–j0.2
–j5
START 950.000 000MHz
NORMALISED TO 50Ω
–j0.5
–j1
–j2
STOP 2 150.000 000 MHz
Figure 3 Input impedance (typical)
4
Preliminary Information
Marker
1
2
3
4
Freq (MHz)
950
1250
1550
2150
Z real
Ω
34
35
58
84
SL1914
Z imag
Ω
-16
2
68
-30
+j1
+j0.5
+j2
+j0.2
+j5
0
0.2
0.5
1
2
5
1
∆
2
–j0.2
∆
–j5
∆
∆
4 3
START 950.000 000MHz
NORMALISED TO 50Ω
–j0.5
–j1
–j2
STOP 2 150.000 000 MHz
Figure 4 Output impedance (typical)
5
FPGA/CPLD
