Preliminary
SL23EP08
Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer (ZDB)
Key Features
10 to 220 MHz operating frequency range
Low output clock skew: 70ps-typ
Low output clock Jitter: 50 ps-typ
- 50 ps-typ at 166MHz, CL=15pF and VDD=3.3V
- 75 ps-typ at 166MHz, CL=15pF and VDD=2.5V
Low part-to-part output skew: 150 ps-typ
3.3V to 2.5V power supply range
Low power dissipation:
- 22 mA-typ at 66MHz and VDD=3.3V
- 20 mA-typ at 66MHz and VDD=2.5V
One input drives 8 outputs
Multiple configurations and drive options
Select mode to bypass PLL or tri-state outputs
SpreadThru™ PLL that allows use of SSCG
Available in 16-pin SOIC and TSSOP packages
Available in Commercial and Industrial grades
Description
The SL23EP08 is a low skew, low jitter and low power
Zero Delay Buffer (ZDB) designed to produce up to eight
(8) clock outputs from one (1) reference input clock, for
high speed clock distribution applications.
The product has an on-chip PLL and a feedback pin (FBK)
which can be used to obtain feedback from any one of the
output clocks. The SL23EP08 has two (2) clock driver
banks each with four (4) clock outputs. These outputs are
controlled by two (2) select input pins S1 and S2. When
only four (4) outputs are needed, bank-B output clock
buffers can be tri-stated to reduce power dissipation and
jitter. The select inputs can also be used to tri-state both
banks A and B or drive them directly from the input
bypassing the PLL and making the product behave like a
Non-Zero Delay Buffer (NZDB). The SL23EP08 offers
various X/2,1X, 2X and 4x frequency options at the output
clocks. Refer to the “Product Configuration Table” for the
details.
The SL23EP08-1H, -2H and 5H versions operates up to
220 MHz and SL23EP08-1, -2, -3 and -4 versions operate
up to 133 MHz with CL=15pF output load.
Applications
Printers, MFPs and Digital Copiers
PCs and Work Stations
Routers, Switchers and Servers
Datacom and Telecom
High-Speed Digital Embeded Systems
Benefits
Up to eight (8) distribution of input clock
Standard and High-Dirive levels to control
impedance level, frequency range and EMI
Low skew, jitter and power dissipation
Block Diagram
/2
(Divider for -3 and -4)
Low Power and
Low Jitter
CLKIN
/2
(Divider for -5H only)
PLL
MUX
FBK
CLKA1
CLKA2
CLKA3
S2
Input Selection
Decoding Logic
S1
/2
(Divider for -2, -2H and -3)
CLKA4
CLKB1
CLKB2
CLKB3
2
2
CLKB4
VDD
GND
Rev 1.4, May 28, 2007
Page 1 of 18
2200 Laurelwood Road, Santa Clara, CA 95054 Tel: (408) 855-0555 Fax: (408) 855-0550 www.SpectraLinear.com
SL23EP08
Pin Configuration
16-Pin SOIC/TSSOP
Pin Description
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin Name
CLKIN
CLKA1
CLKA2
VDD
GND
CLKB1
CLKB2
S2
S1
CLKB3
CLKB4
GND
VDD
CLKA3
CLKA4
FBK
Pin Type
Input
Output
Output
Power
Power
Output
Output
Input
Input
Output
Output
Power
Power
Output
Output
Output
Pin Description
Reference Frequency Clock Input. 5V tolerant input. Weak pull-down
(250k ).
Buffered Clock Output, Bank A. Weak pull-down (250k ).
Buffered Clock Output, Bank A. Weak pull-down (250k ).
3.3V to 2.5V Power Supply.
Power Ground.
Buffered Clock Output, Bank B. Weak pull-down (250k ).
Buffered Clock Output, Bank B. Weak pull-down (250k ).
Select Input, select pin S2. Weak pull-up (250k ).
Select Input, select pin S1. Weak pull-up (250k ).
Buffered Clock Output, Bank B. Weak pull-down (250k ).
Buffered Clock Output, Bank B. Weak pull-down (250k ).
Power Ground.
3.3V to 2.5V Power Supply.
Buffered Clock Output, Bank A. Weak pull-down (250k ).
Buffered Clock Output, Bank A. Weak pull-down (250k ).
PLL Feedback input.
Rev 1.4, May 28, 2007
Page 2 of 18
SL23EP08
General Description
The SL23EP08 is a low skew, low jitter Zero Delay
Buffer with very low operating current.
The product includes an on-chip high performance PLL
that locks into the input reference clock and produces
eight (8) output clock drivers tracking the input
reference clock for systems requiring clock distribution.
in addition to FBK pin used for internal PLL feedback,
there are two (2) banks with four (4) outputs in each
bank, bringing the number of total available output
clocks to eight (8).
PLL Bypass Mode
If the S2=1 and S2=0 pins, the on-chip PLL is shutdown
and bypassed, and all the eight (8) output clocks of bank
A and bank B are driven directly from the reference input
clock. In this operation mode SL23EP08 works like a
non-ZDB product.
High and Low-Drive Product Options
The SL23EP08 is offered with high drive “-1H, -2H and -
5H” and standard drive “-1, -2, -3 and -4” options. These
drive options enable the users to control load levels,
frequency range and EMI control. Refer to the AC
electrical tables for the details.
SL23EP08-5H is offered only with high drive option.
SL23EP08-3 and -4 are offered only with standard drive
option.
Input and output Frequency Range
The input and output frequency range is the same for
SL23EP08-1 and -1H versions. For SL23EP08-2, -2H -
3, -4 and -5H versions, the output frequency is 1/2x,
1x, 2x, or 4x of the CLKIN as given in the “Available
SL23EP08 Configurations” Table 3. But, the frequency
range depends on VDD and drive levels as given in the
“Electrical Specifications” Tables.
If the input clock frequency is DC (from GND to VDD),
this is detected by an input frequency detection
circuitry and all eight (8) clock outputs are forced to Hi-
Z. The PLL is shutdown to save power. In this
shutdown state, the product draws less than 10 A
supply current.
Skew and Zero Delay
All outputs should drive the similar load to achieve
output-to-output skew and input-to-output delay
specifications given in the AC electrical tables. However,
Zero delay between input and outputs can be adjusted
by changing the loading of FBK pin relative to the banks
A and B clocks since FBK is the feedback to the PLL.
Power Supply Range (VDD)
SpreadThru™ Feature
If a Spread Spectrum Clock (SSC) were to be used as
an input clock, the SL23EP08 is designed to pass the
modulated Spread Spectrum Clock (SSC) signal from
its reference input to the output clocks. The same
spread characteristics at the input are passed through
the PLL and drivers without any degradation in spread
percent (%), spread profile and modulation frequency.
The SL23EP08 is designed to operate with from 3.3V to
2.5V VDD power supply range. An internal on-chip
voltage regulator is used to provide PLL constant power
supply of 1.8V, leading to a consistent and stable PLL
electrical performance in terms of skew, jitter and power
dissipation. The SL2308 I/O is powered by using VDD.
Contact SLI for 1.8V power supply version ZDB called
SL23EPL08.
Select Input Control
The SL23EP08 provides two (2) input select control
pins called S1 and S2. This feature enables users to
selects various states of output clock banks-A and
bank-B, output source and PLL shutdown features as
shown in the Table 2.
The S1 (Pin-9) and S2 (Pin-8) inputs include 250 k
weak pull-down resistors to GND.
Rev 1.4, May 28, 2007
Page 3 of 18
SL23EP08
Figure 1. CLKIN Input to CLKA and CLKB Delay
S2
0
0
1
1
S1
0
1
0
1
Clock A1-A4
Tri-state
Driven
Driven
Driven
Clock B1-B4
Tri-state
Tri-state
Driven
Driven
Output Source
PLL
PLL
Reference(CLKIN)
PLL
PLL Shutdown
and Bypass
Yes
No
Yes
No
Table 2. Select Input Decoding
Device
SL23EP08-1 and 1H
SL23EP08-2 and -2H
SL23EP08-2 and -2H
SL23EP08-3
SL23EP08-3
[1]
[1]
[1]
[1]
Feedback From
Bank-A or Bank-B
Bank-A
Bank-B
Bank-A
Bank-B
Bank-A or Bank-B
Bank-A or Bank-B
Bank-A Frequency
Reference
Reference
2x Reference
2xReference
4xReference
2x Reference
Reference/2
Bank-B Frequency
Reference
Reference/2
Reference
Reference
[2]
2xReference
2x Reference
Reference/2
SL23EP08-4
SL23EP08-5H
Table 3. Available SL23EP08 Configurations
Notes:
1. Outputs are inverted on SL23EP08-2, -2H and -3 in PLL bypass mode when S2=1 and S1=0. Use SL23EP08-1 if
non-inverting outputs are required.
2. Output phase is random (0° or 180° with respect to input clock). Use SL23EP08-2 if phase integrity is required.
Rev 1.4, May 28, 2007
Page 4 of 18
SL23EP08
Absolute Maximum Ratings
Description
Supply voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
ESD Rating (Human Body Model)
MIL-STD-883, Method 3015
In operation, C-Grade
In operation, I-Grade
No power is applied
In operation, power is applied
Condition
Min
-0.5
-0.5
0
-40
-65
-
-
2000
Max
4.6
VDD+0.5
70
85
150
125
260
-
Unit
V
V
°C
°C
°C
°C
°C
V
Operating Conditions (C-Grade)
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range 0 to +70°C
Description
Operating Voltage
Operating Temperature
Input Capacitance
Symbol
VDD
TA
VIH
Condition
VDD+/-10%
Ambient Temperature
Pins 1, 8, 9 and 16
Min
2.97
0
-
Typ
3.3
-
5
Max
3.63
70
7
Unit
V
°C
pF
Rev 1.4, May 28, 2007
Page 5 of 18
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