SL4049B
Hex Buffer/Converter
High-Voltage Silicon-Gate CMOS
The SL4049B is inverting hex buffers and feature logic-level
conversion using only one supply (voltage (V
CC
). The input-signal high
level (V
IH
) can exceed the V
CC
supply voltage when these devices are
used for logic-level conversions. These devices are intended for use as
CMOS to DTL/TTL converters.
•
Operating Voltage Range: 3.0 to 18 V
•
Maximum input current of 1
µA
at 18 V over full package-
temperature range; 100 nA at 18 V and 25°C
•
Noise margin (over full package temperature range):
0.5 V min @ 5.0 V supply
1.0 V min @ 10.0 V supply
1.0 V min @ 15.0 V supply
•
High-to-low level conversion
ORDERING INFORMATION
SL4049BN Plastic
SL4049BD SOIC
T
A
= -55° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
NC = NO CONNECTION
FUNCTION TABLE
Inputs
A
H
PINS 13, 16 = NO CONNECTION
PIN 1 =V
CC
PIN 8 = GND
L
Output
Y
L
H
SLS
System Logic
Semiconductor
SL4049B
MAXIMUM RATINGS
*
Symbol
V
CC
V
IN
V
OUT
I
IN
P
D
P
D
Tstg
T
L
*
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
Power Dissipation per Output Transistor
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
Value
-0.5 to +20
V
CC**
to +18
-0.5 to V
CC
+0.5
±10
750
500
100
-65 to +150
260
Unit
V
V
V
mA
mW
mW
°C
°C
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
**
The IW4049UB has high-to-low level voltage conversion capability but not low-to-high level; therefore it is
recommended that V
IN
≥
V
CC
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
V
OUT
T
A
**
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Min
3.0
V
CC**
0
-55
Max
18
18
V
CC
+125
Unit
V
V
V
°C
The SL4049B has high-to-low level voltage conversion capability but not low-to-high level; therefore it is
recommended that V
IN
≥
V
CC
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range
GND≤(V
IN
or V
OUT
)≤V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ).
CC
Unused outputs must be left open.
SLS
System Logic
Semiconductor
SL4049B
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Symbol
V
IH
Parameter
Minimum High-Level
Input Voltage
Maximum Low -Level
Input Voltage
Minimum High-Level
Output Voltage
Maximum Low-Level
Output Voltage
Maximum Input
Leakage Current
Maximum Quiescent
Supply Current
(per Package)
Minimum Output Low
(Sink) Current
Test Conditions
V
OUT
= 0.5V
V
OUT
= 1.0 V
V
OUT
= 1.5V
V
OUT
= V
CC
- 0.5V
V
OUT
= V
CC
- 1.0 V
V
OUT
= V
CC
- 1.5V
V
IN
=GND
V
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
18
5.0
10
15
20
4.5
5
10
15
5.0
5.0
10
15
Guaranteed Limit
≥-55°C
4
8
12.5
1
2
2.5
4.95
9.95
14.95
0.05
0.05
0.05
±0.1
1
2
4
20
3.3
4
10
26
-2.6
-0.81
-2.0
-5.2
25°C
4
8
12.5
1
2
2.5
4.95
9.95
14.95
0.05
0.05
0.05
±0.1
1
2
4
20
2.6
3.2
8
24
-2.1
-0.65
-1.65
-4.3
≤125
°C
4
8
12.5
1
2
2.5
4.95
9.95
14.95
0.05
0.05
0.05
±1.0
30
60
120
600
1.8
2.4
5.6
18
mA
-1.55
-0.48
-1.18
-3.1
Unit
V
V
IL
V
V
OH
V
V
OL
V
IN
= V
CC
V
I
IN
I
CC
V
IN
= GND or V
CC
V
IN
= GND or V
CC
µA
µA
I
OL
V
IN
= GND or V
CC
U
OL
=0.4 V
U
OL
=0.4 V
U
OL
=0.5 V
U
OL
=1.5 V
mA
I
OH
Minimum Output High V
IN
= GND or V
CC
(Source) Current
U
OH
=2.5 V
U
OH
=4.6 V
U
OH
=9.5 V
U
OH
=13.5 V
SLS
System Logic
Semiconductor
SL4049B
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF, R
L
=200kΩ, Input t
r
=t
f
=20 ns)
V
IN
Symbol
t
PLH
Parameter
Maximum Propagation Delay, Input A to
Output Y (Figure 1)
V
5
10
10
15
15
5
10
10
15
15
5
10
15
5
10
15
-
V
CC
V
5
10
5
15
5
5
10
5
15
5
5
10
15
5
10
15
-
Guaranteed Limit
≥-55°C
120
65
90
50
90
65
40
30
30
20
160
80
60
60
40
30
25°C
120
65
90
50
90
65
40
30
30
20
160
80
60
60
40
30
22.5
≤125°C
240
130
180
100
180
130
80
60
60
40
320
160
120
120
80
60
Unit
ns
t
PHL
Maximum Propagation Delay, Input A to
Output Y (Figure 1)
ns
t
TLH
Maximu m Output Transition Time, Any
Output (Figure 1)
Maximum Output Transition Time, Any
Output (Figure 1)
Maximum Input Capacitance
ns
t
THL
ns
C
IN
pF
Figure 1. Switching Waveforms
EXPANDED LOGIC DIAGRAM
(1/6 of the Device)
SLS
System Logic
Semiconductor
