SL4051B
Analog Multiplexer Demultiplexer
High-Performance Silicon-Gate CMOS
The SL4051B analog multiplexer/demultiplexer is digitally controlled
analog switches having low ON impedance and very low OFF leakage
current. Control of analog signals up to 20V peak-to-peak can be
achieved by digital signal amplitudes of 4.5 to 20V (if V
CC
- GND = 3V, a
V
CC
- V
EE
of up to 13 V can be controlled; for V
CC
- V
EE
level differences
above 13V a V
CC
- GND of at least 4.5V is required).
These multiplexer circuits dissipate extremely low quiescent power
over the full V
CC
-GND and V
CC
- V
EE
supply-voltage ranges,
independent of the logic state of the control signals. When a logic
“1”is present at the ENABLE input terminal all channels are off.
The SL4051B is a single 8-channel multiplexer having three binary
control inputs, A,B and C, and an ENABLE input. The three binary
signals select 1 of 8 channels to be turned on, and connect one of the 8
inputs to the output.
•
Operating Voltage Range: 3.0 to 18 V
•
Maximum input current of 1
µA
at 18 V over full package-
temperature range; 100 nA at 18 V and 25°C
•
Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
ORDERING INFORMATION
SL4051BN Plastic
SL4051BD SOIC
T
A
= -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
Single-Pole, 8-Position Plus Common Off
FUNCTION TABLE
Control Inputs
Enable
C
L
L
L
L
L
PIN 16 =V
CC
PIN 7 = V
EE
PIN 8 = GND
L
L
L
H
L
L
L
L
H
H
H
H
X
Select
B
L
L
H
H
L
L
H
H
X
A
L
H
L
H
L
H
L
H
X
X0
X1
X2
X3
X4
X5
X6
X7
None
ON
Channels
X = don’t care
SLS
System Logic
Semiconductor
SL4051B
MAXIMUM RATINGS
*
Symbol
V
CC
V
IN
V
OUT
I
IN
P
D
P
D
Tstg
T
L
*
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
Power Dissipation per Output Transistor
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
Value
-0.5 to +20
-0.5 to V
CC
+0.5
-0.5 to V
CC
+0.5
±10
750
500
100
-65 to +150
260
Unit
V
V
V
mA
mW
mW
°C
°C
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
, V
OUT
T
A
I
R
OH
*
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Multiplexer Switch Input Current Capability
*
Output Load Resistance
Min
3.0
0
-55
-
100
Max
18
V
CC
+125
25
-
Unit
V
V
°C
mA
Ω
In certain applications, the external load-resistor current may include both V
CC
and signal-line components.
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range
GND≤(V
IN
or V
OUT
)≤V
CC
.
Unused digital pins must be tied to an appropriate logic voltage level (e.g., either GND or V
CC
). Unused
Analog I/O pins may be left open or terminated.
SLS
System Logic
Semiconductor
SL4051B
DC ELECTRICAL CHARACTERISTICS
Digital Section
V
CC
Symbol
V
IH
Parameter
Minimum High-Level
Input Voltage, Channel-
Select or Enable Inputs
Maximum Low -Level
Input Voltage, Channel-
Select or Enable Inputs
Maximum Input
Leakage Current,
Channel-Select or
Enable Inputs
Maximum Quiescent
Supply Current (per
Package)
Test Conditions
V
IS
=V
CC
thru 1kΩ
V
EE
=GND
I
IS
<2µA on all OFF Chanels
R
L
=1kΩ to GND
V
IS
=V
CC
thru 1kΩ
V
EE
=GND
I
IS
<2µA on all OFF Chanels
R
L
=1kΩ to GND
V
IN
=V
CC
or GND
V
5
10
15
5
10
15
18
Guaranteed Limit
≥
-55
°C
3.5
7
11
1.5
3
4
±0.1
≤
25
°C
3.5
7
11
1.5
3
4
±0.1
≤
125
°C
3.5
7
11
1.5
3
4
±1.0
Unit
V
V
IL
V
I
IN
µA
I
CC
Channel Select = V
CC
or GND
5
10
15
20
5
10
20
100
5
10
20
100
150
300
600
3000
µA
DC ELECTRICAL CHARACTERISTICS
Analog Section
V
CC
Symbol
R
ON
Parameter
Maximum “ON” Resistance
Test Conditions
V
EE
=GND=0
V
IS
= GND to V
CC
V
EE
=GND=0
V
5
10
15
5
10
15
18
Guaranteed Limit
≥
-55
°C
800
310
200
-
-
-
±100
≤
25
°C
1050
400
240
10
15
5
±100
≤
125
°C
1300
550
320
-
-
-
±1000
Unit
Ω
∆R
ON
Maximum Difference in
“ON” Resistance Between
Any Two Channels in the
Same Package
Maximum Off- Channel
Leakage Current, Any One
Channel
Maximum Off- Channel
Leakage Current, Common
Channel
Ω
I
OFF
V
EE
=GND=0
nA
V
EE
=GND=0
18
±100
±100
±1000
SLS
System Logic
Semiconductor
SL4051B
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=20.0 ns)
V
CC
Symbol
t
PLH
, t
PHL
Parameter
Maximum Propagation Delay , Analog Input to
Analog Output (Figure 1)
R
L
=200kΩ
Maximum Propagation Delay , Address to Analog
Output (Figure 2) R
L
=10kΩ
V
EE
=GND=0
V
EE
=-5V
t
PLZ
,
t
PZL
Maximum Propagation Delay, Enable to Analog
Output (Figure 2) R
L
=10kΩ
V
EE
=GND=0
V
EE
=-10V
t
PHZ
,
t
PZH
Maximum Propagation Delay, Enable to Analog
Output (Figure 2) R
L
=10kΩ
V
EE
=GND=0
V
EE
=-10V
C
IN
C
I/O
Maximum Input Capacitance, Channel-Select or
Enable Inputs
Maximum Capacitance
V
EE
=GND=-5V
C
IS
C
OS
Feedthrough C
IOS
5
5
5
-
-
-
5
30
0.2
-
-
-
pF
V
5
10
15
5
10
15
5
5
10
15
5
5
10
15
5
-
Guaranteed Limit
≥
-55
°C
60
30
20
720
320
240
450
720
320
240
400
450
210
160
300
7.5
≤
25
°C
60
30
20
720
320
240
450
720
320
240
400
450
210
160
300
7.5
≤
125
°C
120
60
40
1440
640
480
900
1440
640
480
800
900
420
320
600
7.5
pF
ns
ns
Unit
ns
t
PLZ
, t
PHZ
ns
SLS
System Logic
Semiconductor
SL4051B
ADDITIONAL APPLICATION CHARACTERISTICS
V
CC
Symbol
Parameter
Maximum On-
Channel
Bandwidth or
Minimum
Frequency
Response (-3db)
Test Conditions
V
EE
=GND
R
L
=1kΩ
20 log(V
OS
/V
IS
)=-3db
10
V
OS
at Common OUT/IN
V
OS
at Any Channel
(-40db)
Feedthrough
Frequency (All
Channels OFF)
V
EE
=GND
R
L
=1kΩ
20 log(V
OS
/V
IS
)=-40db
V
OS
at Common OUT/IN
V
OS
at Any Channel
(-40db)
Signal Crosstalk
Frequency
THD
Total Harmonic
Distortion
Address-or
Enable to Signal
Crosstalk
V
EE
=GND
R
L
=1kΩ
20 log(V
OS
/V
IS
)=-40db
Between Any 2 Channels
V
EE
=GND
f
IS
=1kHz sine wave
V
EE
=GND, R
L
=10kΩ**
t
r
,t
f
=20ns
Square Wave
10
5
*
60
5
*
20
MHz
V
V
IS
V
Limit
*
25
°C
Unit
BW
10
10
5
*
5
*
12
8
10
5
10
15
10
5
*
2*
3*
5*
-
3
0.3
0.2
012
65
%
-
mv
(Peak)
* Peak-to-peak voltage symmetrical about (V
CC
-V
EE
)/2.
** Both ends of channel.
SLS
System Logic
Semiconductor
