SL4069UB
Hex Inverter
High-Voltage Silicon-Gate CMOS
The SL4069UB types consist of six inverter circuits. These devices
are intended for all general-purpose inverter applications where the
medium-power TTL-drive and logic-level-conversion capabilities of
circuits such as the SL4049UB Hex Inverter/Buffers are not required.
Each of the six inverters is a single stage
•
Operating Voltage Range: 3.0 to 18 V
•
Maximum input current of 1
µA
at 18 V over full package-
temperature range; 100 nA at 18 V and 25°C
•
Noise margin (over full package temperature range):
0.5 V min @ 5.0 V supply
1.0 V min @ 10.0 V supply
1.0 V min @ 15.0 V supply
ORDERING INFORMATION
SL4069UBN Plastic
SL4069UBD SOIC
T
A
= -55° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
FUNCTION TABLE
Inputs
A
L
H
PIN 14 =V
CC
PIN 7 = GND
Output
Y
H
L
SLS
System Logic
Semiconductor
SL4069UB
MAXIMUM RATINGS
*
Symbol
V
CC
V
IN
V
OUT
I
IN
P
D
P
D
Tstg
T
L
*
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
Power Dissipation per Output Transistor
Storage Temp erature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
Value
-0.5 to +20
-0.5 to V
CC
+0.5
-0.5 to V
CC
+0.5
±10
750
500
100
-65 to +150
260
Unit
V
V
V
mA
mW
mW
°C
°C
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
, V
OUT
T
A
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Min
3.0
0
-55
Max
18
V
CC
+125
Unit
V
V
°C
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range
GND≤(V
IN
or V
OUT
)≤V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ).
CC
Unused outputs must be left open.
SLS
System Logic
Semiconductor
SL4069UB
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Symbol
V
IH
Parameter
Minimum High-Level
Input Vo ltage
Maximum Low -Level
Input Voltage
Minimum High-Level
Output Voltage
Maximum Low-Level
Output Voltage
Maximum Input
Leakage Current
Maximum Quiescent
Supply Current
(per Package)
Minimum Output Low
(Sink) Current
Test Conditions
V
OUT
=0.5V
V
OUT
=1.0 V
V
OUT
=1.5V
V
OUT
= V
CC
- 0.5 V
V
OUT
= V
CC
- 1 V
V
OUT
= V
CC
- 1.5 V
V
IN
=GND
V
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
18
5.0
10
15
20
5.0
10
15
5.0
5.0
10
15
Guaranteed Limit
≥-55°C
4
8
12.5
1
2
2.5
4.95
9.95
14.95
0.05
0.05
0.05
±0.1
0.25
0.5
1.0
5.0
0.64
1.6
4.2
-2.0
-0.64
-1.6
-4.2
25°C
4
8
12.5
1
2
2.5
4.95
9.95
14.95
0.05
0.05
0.05
±0.1
0.25
0.5
1.0
5.0
0.51
1.3
3.4
-1.6
-0.51
-1.3
-3.4
≤125
°C
4
8
12.5
1
2
2.5
4.95
9.95
14.95
0.05
0.05
0.05
±1.0
7.5
15
30
150
0.36
0.9
2.4
mA
-1.15
-0.36
-0.9
-2.4
Unit
V
V
IL
V
V
OH
V
V
OL
V
IN
= V
CC
V
I
IN
I
CC
V
IN
= GND or V
CC
V
IN
= GND or V
CC
µA
µA
I
OL
V
IN
= GND or V
CC
U
OL
=0.4 V
U
OL
=0.5 V
U
OL
=1.5 V
mA
I
OH
Minimum Output High V
IN
= GND or V
CC
(Source) Current
U
OH
=2.5 V
U
OH
=4.6 V
U
OH
=9.5 V
U
OH
=13.5 V
SLS
System Logic
Semiconductor
SL4069UB
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF, R
L
=200kΩ, Input t
r
=t
f
=20 ns)
V
CC
Symbol
t
PLH
, t
PHL
Parameter
Maximum Propagation Delay, Input A to Output
Y (Figure 1)
Maximum Output Transition Time, Any Output
(Figure 1)
Maximum Input Capacitance
V
5.0
10
15
5.0
10
15
-
Guaranteed Limit
≥-55°C
110
60
50
200
100
80
25°C
110
60
50
200
100
80
15
≤125°C
220
120
100
400
200
160
Unit
ns
t
TLH
, t
THL
ns
C
IN
pF
Figure 1. Switching Waveforms
EXPANDED LOGIC DIAGRAM
(1/6 of the Device)
SLS
System Logic
Semiconductor
