SL74HC154
1- of-16 Decoder/Demultiplexer
High-Performance Silicon-Gate CMOS
The SL74HC154 is identical in pinout to the LS/ALS154. The
device inputs are compatible with standard CMOS outputs; with
pullup resistors, they are compatible with LS/ALSTTL outputs.
This device, when enabled, selects one of 16 active-low outputs.
Two active-low Chip Selects are provided to facilitate the chip-select,
demultiplexing, and cascading functions. When either Chip Select is
high, all outputs are high. The demultiplexing function is
accomplished by using the Address inputs to select the desired
device output.
The SL74HC154 is primarily used for memory address decoding
and data routing applications.
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 2.0 to 6.0 V
•
Low Input Current: 1.0
µA
•
High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
SL74HC154N Plastic
SL74HC154D SOIC
T
A
= -55° to 125° C for all
packages
LOGIC DIAGRAM
PIN ASSIGNMENT
PIN 24 =V
CC
PIN 12 = GND
SLS
System Logic
Semiconductor
SL74HC154
MAXIMUM RATINGS
*
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
I
CC
P
D
Tstg
T
L
*
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
Value
-0.5 to +7.0
-1.5 to V
CC
+1.5
-0.5 to V
CC
+0.5
±20
±25
±50
750
500
-65 to +150
260
Unit
V
V
V
mA
mA
mA
mW
°C
°C
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
, V
OUT
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
V
CC
=2.0 V
V
CC
=4.5 V
V
CC
=6.0 V
Min
2.0
0
-55
0
0
0
Max
6.0
V
CC
+125
1000
500
400
Unit
V
V
°C
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range
GND≤(V
IN
or V
OUT
)≤V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ).
CC
Unused outputs must be left open.
SLS
System Logic
Semiconductor
SL74HC154
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Symbol
Parameter
Test Conditions
V
Guaranteed Limit
25
°C
to
-55°C
1.5
3.15
4.2
0.3
0.9
1.2
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
±0.1
8.0
≤85
°C
1.5
3.15
4.2
0.3
0.9
1.2
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±1.0
80
≤125
°C
1.5
3.15
4.2
0.3
0.9
1.2
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±1.0
160
µA
µA
V
Unit
V
IH
Minimum High-Level
Input Voltage
Maximum Low -Level
Input Voltage
Minimum High-Level
Output Voltage
V
OUT
=0.1 V or V
CC
-0.1 V
I
OUT
≤
20
µA
V
OUT
=0.1 V or V
CC
-0.1 V
I
OUT
≤
20
µA
V
IN
=V
IH
or V
IL
I
OUT
≤
20
µA
V
IN
=V
IH
or V
IL
I
OUT
≤
4.0 mA
I
OUT
≤
5.2 mA
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
V
V
IL
V
V
OH
V
V
OL
Maximum Low-Level
Output Voltage
V
IN
=V
IH
or V
IL
I
OUT
≤
20
µA
V
IN
=V
IH
or V
IL
I
OUT
≤
4.0 mA
I
OUT
≤.5.2
mA
I
IN
I
CC
Maximum Input
Leakage Current
Maximum Quiescent
Supply Current
(per Package)
V
IN
=V
CC
or GND
V
IN
=V
CC
or GND
I
OUT
=0µA
SLS
System Logic
Semiconductor
SL74HC154
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Symbol
t
PLH
, t
PHL
Parameter
Maximum Propagation Delay, Input A to
Output Y (Figures 1and 3)
Maximum Propagation Delay , CS to
Output Y (Figures 2 and 3)
Maximum Output Transition Time, Any Output
(Figures 2 and 3)
Maximum Input Capacitance
Power Dissipation Capacitance (Per Package)
C
PD
Used to determine the no-load dynamic power
consumption: P
D
=C
PD
V
CC2
f+I
CC
V
CC
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
-
Guaranteed Limit
25
°C
to
-55°C
190
38
32
175
35
30
75
15
13
10
≤85°C
240
48
41
220
44
37
95
19
16
10
≤125°C
285
57
48
265
53
45
110
22
19
10
Unit
ns
t
PLH
, t
PHL
ns
t
TLH
, t
THL
ns
C
IN
pF
Typical @25°C,V
CC
=5.0 V
80
pF
FUNCTION TABLE
Inputs
CS1 CS2 A3 A2 A1 A0 Y0
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
X
X
X
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
X
X
X
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
X
X
X
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X
X
X
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Y1
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Y2
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Y3
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Y4
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Y5
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
Y6
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
Outputs
Y7
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
Y8
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
Y9 Y10 Y11 Y12 Y13 Y14 Y15
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
SLS
System Logic
Semiconductor
SL74HC154
X = Don’t Care
SLS
System Logic
Semiconductor
