SL74HC158
Quad 2-Input Data Selectors/Multiplexers
High-Performance Silicon-Gate CMOS
The SL74HC158 is identical in pinout to the LS/ALS158. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
This device routes 2 nibbles (A or B) to a single port (Y) as
determined by the Select input. The data is presented at the outputs in
invertered form. A high level on the Output Enable input sets all four Y
outputs to a high level.
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 2.0 to 6.0 V
•
Low Input Current: 1.0
µA
•
High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
SL74HC158N Plastic
SL74HC158D SOIC
T
A
= -55° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
FUNCTION TABLE
Inputs
PIN 16 =V
CC
PIN 8 = GND
Output
Enable
H
L
L
Select
X
L
H
Outputs
Y0-Y3
H
A0-A3
B0-B3
X=don’t care
A0-A3,B0-B3=the levels of the respective
Data-Word Inputs
SLS
System Logic
Semiconductor
SL74HC158
MAXIMUM RATINGS
*
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
I
CC
P
D
Tstg
T
L
*
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
Value
-0.5 to +7.0
-1.5 to V
CC
+1.5
-0.5 to V
CC
+0.5
±20
±25
±50
750
500
-65 to +150
260
Unit
V
V
V
mA
mA
mA
mW
°C
°C
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
, V
OUT
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
V
CC
=2.0 V
V
CC
=4.5 V
V
CC
=6.0 V
Min
2.0
0
-55
0
0
0
Max
6.0
V
CC
+125
1000
500
400
Unit
V
V
°C
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range
GND≤(V
IN
or V
OUT
)≤V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ).
CC
Unused outputs must be left open.
SLS
System Logic
Semiconductor
SL74HC158
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Symbol
Parameter
Test Conditions
V
Guaranteed Limit
25
°C
to
-55°C
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
±0.1
4.0
≤85
°C
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±1.0
40
≤125
°C
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±1.0
160
µA
µA
V
Unit
V
IH
Minimum High-Level
Input Voltage
Maximum Low -Level
Input Voltage
Minimum High-Level
Output Voltage
V
OUT
=0.1 V or V
CC
-0.1 V
I
OUT
≤
20
µA
V
OUT
=0.1 V or V
CC
-0.1 V
I
OUT
≤
20
µA
V
IN
=V
IH
or V
IL
I
OUT
≤
20
µA
V
IN
=V
IH
or V
IL
I
OUT
≤
4.0 mA
I
OUT
≤
5.2 mA
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
V
V
IL
V
V
OH
V
V
OL
Maximum Low-Level
Output Voltage
V
IN
=V
IH
or V
IL
I
OUT
≤
20
µA
V
IN
=V
IH
or V
IL
I
OUT
≤
4.0 mA
I
OUT
≤
5.2 mA
I
IN
I
CC
Maximum Input
Leakage Current
Maximum Quiescent
Supply Current
(per Package)
V
IN
=V
CC
or GND
V
IN
=V
CC
or GND
I
OUT
=0µA
SLS
System Logic
Semiconductor
SL74HC158
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Symbol
t
PLH
, t
PHL
Parameter
Maximum Propagation Delay, Input A or B to
Output Y (Figures 1and 4)
Maximum Propagation Delay , Select to
Output Y (Figures 2 and 4)
Maximum Propagation Delay , Output Enable to
Output Y (Figures 3 and 4)
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
Maximum Input Capacitance
Power Dissipation Capacitance (Per Package)
C
PD
Used to determine the no-load dynamic power
consumption:
P
D
=C
PD
V
CC2
f+I
CC
V
CC
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
-
Guaranteed Limit
25
°C
to
-55°C
105
21
18
110
22
19
100
20
17
75
15
13
10
≤85°C
130
26
22
140
28
24
125
25
21
95
19
16
10
≤125°C
160
32
27
165
33
28
150
30
26
110
22
19
10
Unit
ns
t
PLH
, t
PHL
ns
t
PLH
, t
PHL
ns
t
TLH
, t
THL
ns
C
IN
pF
Typical @25°C,V
CC
=5.0 V
33
pF
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Test Circuit
SLS
System Logic
Semiconductor
SL74HC158
EXPANDED LOGIC DIAGRAM
SLS
System Logic
Semiconductor
