SL74HC4053
Analog Multiplexer/Demultiplexer
High-Performance Silicon-Gate CMOS
The SL74HC4053 utilize silicon-gate CMOS technology to achieve
fast propagation delays, low ON resistances, and low OFF leakage
currents. These analog multiplexers/demultiplexers control analog
voltages that may vary across the complete power supply range (from
V
CC
to V
EE
).
The Channel-Select inputs determine which one of the Analog
Inputs/Outputs is to be connected, by means of an analog switch, to
the Common Output/Input.When the Enable pin is high, all analog
switches are turned off.
The Channel-Select and Enable inputs are compatible with standard
CMOS outputs; with pullup resistors, they are compatible with
LS/ALSTTL outputs.
•
Fast Switching and Propagation Speeds
•
Low Crosstalk Between Switches
•
Diode Protection on All Inputs/Outputs
•
Analog Power Supply Range (V
CC
-V
EE
)=2.0 to 12.0 V
•
Digital (Control) Power Supply Range (V
CC
-GND)=2.0 to 6.0 V
•
Low Noise
ORDERING INFORMATION
SL74HC4053N Plastic
SL74HC4053D SOIC
T
A
= -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
Triple Single-Pole, Double-Position
Plus Common Off
FUNCTION TABLE
Control Inputs
Enable
C
L
L
L
L
PIN 16 =V
CC
PIN 7 = V
EE
PIN 8 = GND
L
L
L
L
H
L
L
L
L
H
H
H
H
X
Select
B
L
L
H
H
L
L
H
H
X
A
L
H
L
H
L
H
L
H
X
Z0
Z0
Z0
Z0
Z1
Z1
Z1
Z1
Y0
Y0
Y1
Y1
Y0
Y0
Y1
Y1
None
X0
X1
X0
X1
X0
X1
X0
X1
ON
Channels
X = don’t care
SLS
System Logic
Semiconductor
SL74HC4053
MAXIMUM RATINGS
*
Symbol
V
CC
V
EE
V
IS
V
IN
I
P
D
Tstg
T
L
*
Parameter
Positive DC Supply Voltage (Referenced to GND)
(Referenced to V
EE
)
Negative DC Supply Voltage (Referenced to GND)
Analog Input Voltage
Digital Input Voltage (Referenced to GND)
DC Input Current Into or Out of Any Pin
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
Value
-0.5 to +7.0
-0.5 to +14.0
-7.0 to +0.5
V
EE
- 0.5 to V
CC
+0.5
-1.5 to V
CC
+1.5
±25
750
500
-65 to +150
260
Unit
V
V
V
V
mA
mW
°C
°C
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
EE
V
IS
V
IN
V
IO*
T
A
t
r
, t
f
Parameter
Positive Supply Voltage (Referenced to GND)
(Referenced to V
EE
)
Negative DC Supply Voltage (Referenced to GND)
Analog Input Voltage
Digital Input Voltage (Referenced to GND)
Static or Dynamic Voltage Across Switch
Operating Temperature, All Package Types
Input Rise and Fall Time (Channel Select
or Enable Inputs)
V
CC
=2.0 V
V
CC
=4.5 V
V
CC
=6.0 V
Min
2.0
2.0
- 6.0
V
EE
GND
-
-55
0
0
0
Max
6.0
12.0
GND
V
CC
V
CC
1.2
+125
1000
500
400
Unit
V
V
V
V
V
°C
ns
*
For voltage drops across the switch greater than 1.2 V (switch on), excessive V current may be drawn;
CC
i. e., the current out of the switch may contain both V
CC
and switch input components. The reliability of the
device will be unaffected unless the Maximum Ratings are exceeded.
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range
indicated in the Recommended Operating Conditions..
Unused digital input pins must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
).
Unused Analog I/O pins may be left open or terminated.
SLS
System Logic
Semiconductor
SL74HC4053
DC ELECTRICAL CHARACTERISTICS
Digital Section (Voltages Referenced to GND) V
EE
=GND,
Except Where Noted
V
CC
Symbol
V
IH
Parameter
Minimum High-Level
Input Voltage, Channel-
Select or Enable Inputs
Maximum Low -Level
Input Voltage, Channel-
Select or Enable Inputs
Maximum Input
Leakage Current,
Channel-Select or
Enable Inputs
Maximum Quiescent
Supply Current
(per Package)
Test Conditions
R
ON
= Per Spec
V
2.0
4.5
6.0
2.0
4.5
6.0
6.0
Guaranteed Limit
25
°C
to
-55°C
1.5
3.15
4.2
0.3
0.9
1.2
±0.1
≤85
°C
1.5
3.15
4.2
0.3
0.9
1.2
±1.0
≤125
°C
1.5
3.15
4.2
0.3
0.9
1.2
±1.0
Unit
V
V
IL
R
ON
= Per Spec
V
I
IN
V
IN
=V
CC
or GND,
V
EE
=-6.0 V
µA
I
CC
Channel Select = V
CC
or GND
Enable = V
CC
or GND
V
IS
= V
CC
or GND
V
IO
= 0 V
V
EE
= GND
V
EE
= -6.0
µA
6.0
6.0
2
8
20
80
40
160
DC ELECTRICAL CHARACTERISTICS
Analog Section
V
CC
Symbol
Parameter
Test Conditions
V
V
EE
V
Guaranteed Limit
25
°C
to
-55°C
190
120
100
150
100
80
30
12
10
0.1
≤85
°C
240
150
125
190
125
100
35
15
12
0.5
≤125
°C
280
170
140
230
140
115
40
18
14
1.0
Ω
Unit
R
ON
Maximum “ON” Resistance
V
IN
=V
IL
or V
IH
V
IS
= V
CC
or V
EE
I
S
≤
2.0 mA(Figure 1)
V
IN
=V
IL
or V
IH
V
IS
= V
CC
or V
EE
(Endpoints)
I
S
≤
2.0 mA(Figure 1)
4.5
4.5
6.0
4.5
4.5
6.0
4.5
4.5
6.0
6.0
0.0
-4.5
-6.0
0.0
-4.5
-6.0
0.0
-4.5
-6.0
-6.0
Ω
∆R
ON
Maximum Difference in
“ON” Resistance Between
Any Two Channels in the
Same Package
Maximum Off- Channel
Leakage Current, Any One
Channel
Maximum Off- Channel
Leakage Current, Common
Channel
V
IN
=V
IL
or V
IH
V
IS
= 1/2 (V
CC
- V
EE
)
I
S
≤
2.0 mA
V
IN
=V
IL
or V
IH
V
IO
= V
CC
- V
EE
Switch Off (Figure 2)
V
IN
=V
IL
or V
IH
V
IO
= V
CC
- V
EE
Switch Off (Figure 3)
V
IN
=V
IL
or V
IH
Switch to Switch =
V
CC
- V
EE
(Figure 5)
I
OFF
µA
6.0
-6.0
0.1
1.0
2.0
I
ON
Maximum On- Channel
Leakage Current, Channel to
Channel
6.0
-6.0
0.1
1.0
2.0
µA
SLS
System Logic
Semiconductor
SL74HC4053
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Symbol
t
PLH
, t
PHL
Parameter
Maximum Propagation Delay, Channel-Select to
Analog Output (Figures 8 and 9)
Maximum Propagation Delay , Analog Input to
Analog Output (Figures 10 and 11)
Maximum Propagation Delay , Enable to Analog
Output (Figures 12 and 13)
Maximum Propagation Delay , Enable to Analog
Output (Figures 12 and 13)
Maximum Input Capacitance, Channel-Select or
Enable Inputs
Maximum Capacitance
Analog I/O
Common O/I
Feedthrough
Power Dissipation Capacitance (Per Package)
(Figure 15)
C
PD
Used to determine the no-load dynamic power
consumption:
P
D
=C
PD
V
CC2
f+I
CC
V
CC
All Switches Off
-
-
50
1.0
50
1.0
50
1.0
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
-
-
Guaranteed Limit
25
°C
to
-55°C
370
74
63
60
12
10
290
58
49
345
69
59
10
35
≤85°C
465
93
79
75
15
13
364
73
62
435
87
74
10
35
≤125°C
550
110
94
90
18
15
430
86
73
515
103
87
10
35
Unit
ns
t
PLH
, t
PHL
ns
t
PLZ
, t
PHZ
ns
t
PZL
, t
PZH
ns
C
IN
C
I/O
pF
pF
Typical @25°C,V
CC
=5.0 V, V
EE
=0 V
45
pF
SLS
System Logic
Semiconductor
SL74HC4053
ADDITIONAL APPLICATION CHARACTERISTICS
(GND = 0.0 V)
V
CC
Symbol
BW
Parameter
Maximum On-
Channel
Bandwidth or
Minimum
Frequency
Response
(Figure 5)
Off-Channel
Feedthrough
Isolation
(Figure 6)
Test Conditions
f
in
=1 MHz Sine Wave
Adjust f
in
Voltage to Obtain 0 dBm at V
OS
Increase f
in
Frequence Until dB Meter
Reads -3 dB
R
L
=50
Ω,
C
L
=10 pF
V
V
EE
V
Limit
*
25
°C
Unit
MHz
2.25
4.50
6.00
-2.25
-4.50
-6.00
120
120
120
-
f
in
= Sine Wave
Adjust f
in
Voltage to Obtain 0 dBm at V
IS
f
in
= 10 kHz, R
L
=600
Ω,
C
L
=50 pF
f
in
= 1.0 MHz, R
L
=50
Ω,
C
L
=10 pF
dB
2.25
4.50
6.00
2.25
4.50
6.00
-2.25
-4.50
-6.00
-2.25
-4.50
-6.00
-50
-50
-50
-40
-40
-40
mVpp
-
Feedthrough
Noise, Channel
Select Input to
Common O/I
(Figure 7)
V
IN
≤
1 MHz Square Wave (t
r
= t
f
= 6 ns)
Adjust R
L
at Setup so that I
S
= 0 A Enable =
GND
R
L
=600
Ω,
C
L
=50 pF
2.25
4.50
6.00
2.25
4.50
6.00
2.25
4.50
6.00
2.25
4.50
6.00
-2.25
-4.50
-6.00
-2.25
-4.50
-6.00
-2.25
-4.50
-6.00
-2.25
-4.50
-6.00
25
105
135
35
145
190
dB
-50
-50
-50
-60
-60
-60
%
R
L
=10
Ω,
C
L
=10 pF
-
Crosstalk
Between Any
Two Switches
(Figure 14)
f
in
= Sine Wave
Adjust f
in
Voltage to Obtain 0 dBm at V
IS
f
in
= 10 kHz, R
L
=600
Ω,
C
L
=50 pF
f
in
= 1 MHz, R
L
=50
Ω,
C
L
=10 pF
THD
Total Harmonic
Distortion
(Figure 16)
f
in
= 1 kHz, R
L
=10 kΩ, C
L
=50 pF
THD = THD
Measured
- THD
Source
V
IS
=4.0 V
PP
sine wave
V
IS
=8.0 V
PP
sine wave
V
IS
=11.0 V
PP
sine wave
2.25
4.50
6.00
-2.25
-4.50
-6.00
0.10
0.08
0.05
* Limits not tested. Determined by design and verified by qualification.
SLS
System Logic
Semiconductor
