TECHNICAL DATA
SL74LV04
Hex Inverter
The SL74LV04 is a low-voltage Si-gate CMOS device that is pin and
function compatible with 74HC/HCT04A.
The SL74LV04 provides six inverting buffers.
•
•
•
•
Wide Operating Voltage: 1.0 ~ 5.5 V
Optimized for Low Voltage applications: 1.0 ~ 3.6 V
Accepts TTL input levels between V
CC
=2.7 V and V
CC
=3.6 V
Low Input Current
ORDERING INFORMATION
SL74LV04N Plastic
SL74LV04D SOIC
SL74LV04
Chip
T
A
= -40° ÷ 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
FUNCTION TABLE
Input
A
L
H
Output
Y
H
L
PIN 14 =V
CC
PIN 7 = GND
SLS
System Logic
Semiconductor
1
SL74LV04
MAXIMUM RATINGS
*
Symbol
V
CC
I
IK
*
1
I
OK
*
2
Io*
3
I
GND
I
CC
P
D
Tstg
T
L
*
Parameter
DC supply voltage (Referenced to GND)
DC input diode current
DC output diode current
DC output source or sink current
-bus driver outputs
DC GND current for types with
- bus driver outputs
DC V
CC
current for types with
- bus driver outputs
Power dissipation per package, plastic DIP+
SOIC package+
Storage temperature
Lead temperature, 1.5 mm from Case for 10 seconds
(Plastic DIP ), 0.3 mm (SOIC Package)
Value
-0.5 ~ +7.0
±20
±50
±25
±50
±50
750
500
-65 ~ +150
260
Unit
V
mA
mA
mA
mA
mA
mW
°C
°C
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C
SOIC Package: : - 8 mW/°C from 70° to 125°C
1
* : V
I
<
-0.5V or V
I
>
V
CC
+0.5V
*
2
: Vo
<
-0.5V or Vo
>
V
CC
+0.5V
*
3
: -0.5V
<
Vo
<
V
CC
+0.5V
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
, V
OUT
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time
V
CC
=1.2 V
V
CC
=2.0 V
V
CC
=3.0 V
V
CC
=3.6 V
Min
1.0
0
-40
0
0
0
0
Max
5.5
V
CC
+125
1000
700
500
400
Unit
V
V
°C
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V and V
OUT
should be constrained to the range
IN
GND≤(V
IN
or V
OUT
)≤V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
). Unused
outputs must be left open.
SLS
System Logic
Semiconductor
2
SL74LV04
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
V
CC
,
V
min
V
IH
High-Level Input
Voltage
1.2
2.0
3.0
3.6
1.2
2.0
3.0
3.6
1.2
2.0
*
*
1.2
2.0
3.0
0.9
1.4
2.1
2.5
-
-
-
-
1.1
1.92
2.92
2.48
-
-
-
-
max
-
-
-
-
0.3
0.6
0.9
1.1
-
-
-
-
0.09
0.09
0.09
0.33
min
0.9
1.4
2.1
2.5
-
-
-
-
1.0
1.9
2.9
2.34
-
-
-
-
max
-
-
-
-
0.3
0.6
0.9
1.1
-
-
-
-
0.1
0.1
0.1
0.4
25°C
-40°C
÷
85°C
-40°C
÷
125°C
min
0.9
1.4
2.1
2.5
-
-
-
-
1.0
1.9
2.9
2.20
-
-
-
-
max
-
-
-
-
0.3
0.6
0.9
1.1
-
-
-
-
0.1
0.1
0.1
0.5
V
Unit
V
IL
Low-Level Input
Voltage
V
V
OH
High-Level Output V
I
= V
IL
Voltage
I
O
= -50
µA
V
I
= V
IL
I
O
= -6.0
µA
V
V
V
V
OL
Low-Level Output V
I
= V
IH
Voltage
I
O
= 50
µA
V
I
= V
IH
or V
IL
I
O
= 6.0 mÀ
V
I
IL
I
IÍ
I
ÑÑ
Low-Level Input
Leakage Current
High-Level Input V
I
= V
CC
Leakage Current
Quiescent Supply V
I
= 0 Â or V
CC
Current
I
O
= 0
µA
(per Package)
*
*
-
-
-
-0.1
0.1
2.0
-
-
-
-1.0
1.0
20
-
-
-
-1.0
1.0
40
µA
µA
µA
* : V
CC
= (3.3±0.3) V
SLS
System Logic
Semiconductor
3
SL74LV04
AC ELECTRICAL CHARACTERISTICS
(C
L
=50 pF, t
LH
= t
HL
= 6.0 ns, V
IL
=0V, V
IH
=V
CC,
R
L
=1 kÙ)
V
CC
Symbol
Parameter
V
min
t
THL,
(t
TLH)
Output Transition
Time, Any Output
(Figure 1)
Propagation Delay,
Input A to Output Y
(Figure 1)
Input Capacitance
1.2
2.0
*
1.2
2.0
*
3.0
-
-
-
-
-
-
25°C
max
70
16
10
90
23
14
-
Guaranteed Limit
-40°C ÷ 85°C
min
-
-
-
-
-
-
-
max
85
20
13
120
28
18
3.5
-40°C ÷ 125°C
min
-
-
-
-
-
-
-
max
100
24
15
150
34
21
3.5
pF
pF
ns
Unit
t
PHL,
(t
PLH)
C
I
C
PD
Power Dissipation Capacitance (Per Inverter)
Ò
À
=25°Ñ, V
I
=0V÷V
CC
42
Used to determine the no-load dynamic power consumption:
P
D
= C
PD
V
CC2
f
I
+ (C
L
V
CC2
fo), f
I
- input frequency, fo - output frequency (MHz)
(C
L
V
CC2
fo) – sum of the outputs
t
HL
t
LH
V
CC
Input À
0.1
0.9
V
1
0.9
V
1
0.1
t
PHL
0.9
t
PLH
0.9
V
1
0.1
0.1
GND
V
CC
Output Y
V
1
= 0.5 V
C C
V
1
t
THL
t
TLH
GND
Figure 1. Switching Waveforms
V
CC
V
I
PULSE
GENERATOR
R
T
DEVICE
UNDER
TEST
V
O
Termination resistance R
T
– should
be equal to Z
OUT
of pulse
generators
C
L
R
L
Figure 2. Test Circuit
SLS
System Logic
Semiconductor
4
SL74LV04
CHIP PAD DIAGRAM SL74LV04
12
13
11
10
09
08
14
07
06
01
02
03
04
05
1.35
±
0.03
Pad size 0.108 x 0.108 mm (Pad size is given as per
metallization
layer)
Thickness of chip 0.46
±
0,02 mm
PAD LOCATION
Pad No
01
02
03
04
05
06
07
08
09
10
11
12
13
14
Symbol
À1
Y1
A2
Y2
A3
Y3
GND
Y4
A4
Y5
A5
Y6
A6
Vcc
X
0.111
0.333
0.600
0.770
1.006
1.138
1.138
1.138
1.006
0.771
0.600
0.332
0.111
0.111
Y
0.228
0.111
0.111
0.111
0.111
0.293
0.477
0.786
0.970
0.970
0.970
0.970
0.855
0.619
SLS
System Logic
Semiconductor
1.20
±
0.03
Chip marking
25LV04
(x=0.127; y=0.580
)
5
