SM5158A
NIPPON PRECISION CIRCUITS INC.
Serial input PLL frequency synthesizer
PIN OUT
16-pin SSOP
OVERVIEW
The SM5158A is a serial data programma-
ble PLL Frequency Synthesizer LSI fabricated
in NPC's proprietary Molybdenum-gate
CMOS technology.
Ratios of reference frequency divider and
input frequency divider can be independently
set.
FEATURES
- Up to 200MHz input frequency
(VDD=4.5V)
- Up to 35MHz reference frequency
(VDD=4.5V)
- 5 to 65535 programmable reference
frequency divider ratio
- 1056 to 65535 programmable input
frequency divider ratio
- Lock detector
- Either Active or Passive filter can be
externally used.
- 16-pin plastic DIP and 16-pin S-SOP
- Molybdenum gate CMOS structure
XIN
XOUT
FV
VDD
DOP
VSS
LD
FIN
1
16
8
9
OR
OV
TEST
FR
DOA
LE
DATA
CLK
158A
16-pin DIP
XIN
XOUT
FV
VDD
DOP
VSS
LD
FIN
1
16
8
9
OR
OV
TEST
FR
DOA
LE
DATA
CLK
NIPPON PRECISION CIRCUITS-1
SM158AP
SM5158AS
BLOCK DIAGRAM
XIN
XOUT
16 BIT COUNTER
LOCK
DETECTOR
FR
LD
DOA
DOP
OR
16 BIT LATCH
DATA
CLK
17 BIT SHIFT REGISTER
PHASE
DETECTOR
CHARGE
PUMP
LE
FIN
16 BIT LATCH
BUFFER
OV
FV
16 BIT N COUNTER
PIN DESCRIPTION
Number
1
2
3
4
5
6
7
8
Name
XIN
XOUT
FV
VDD
DOP
VSS
LD
FIN
Description
To connect external crystal and capacitor, or external clock input pin.
To connect external crystal and capacitor,or oscilator output signal can be available at this pin.
Buffered input frequency divider output.phase detector input
Positive supply pin. Apply +2.7 to 5.5 Volts.
Charge pump output for passive lowpass filter. Single ended tristate output.
Ground.
Lock detector output. Logic Low when PLL is unlocked.
Comparison frequency input.Internal feedback resistor for AC coupling.
Input frequency range 20MHz to 200MHz.
9
10
11
12
13
14
15
16
CLK
DATA
LE
DOA
FR
TEST
OV
OR
Shift register clock input.
Serial data input.
Latch enable input.
Chrage pump output for active lowpass filter. Single ended tristate output.
Buffered reference frequency devider output. Phase detector input.
Test pin. Left open.
Buffered phase detector output to a differential lowpass filter.
Buffered phase detector output to a differential lowpass filter.
NIPPON PRECISION CIRCUITS-2
SM5158A
SPECIFICATION
Absolute Maximum Ratings
Parameter
Supply voltage range
Input voltage range
Operating temperature range
Storange temperature
Solding temperature
Solding time
Symbol
V
DD
- V
SS
V
IN
T
OPR
Tstg
Tsld
Rating
-0.3 to 7.0
V
SS
-0.3 to V
DD
+0.3
-30 to +85
-40 to 125
255
10
Unit
V
V
deg.C
deg.C
deg.C
S
t
sld
Electrical Characteristics
Rating
Parameter
Supply Voltage
Supply current in operating mode
Symbol
V
DD
I
DD
Condition
F
IN
200MHz , V
FIN
=0.5Vp-p sine wave
X
IN
=20MHz, V
FIN
=0.5Vp-p sine wave
min
2.7
typ
max
5.5
Unit
V
mA
10
23.5
Supply current in stanby mode
FIN maximum operating frequency
I
DD2
fmax1
R/N latch's all bits="0"
F
IN
=0.5Vp-p , sine wave (V
DD
=2.7V)
F
IN
=0.5Vp-p , sine wave (V
DD
=4.5V)
-
100
200
20
35
-
120
240
10
uA
XIN maximum operating frequency
fmax2
X
IN
=0.5Vp-p , sine wave(V
DD
=2.7V)
X
IN
=0.5Vp-p , sine wave(V
DD
=4.5V)
MHz
FIN minimum operating frequency
XIN minimum operating frequency
FIN input voltage
XIN input voltage
CLK, DATA, LE HIGH-level input voltage
CLK, DATA, LE LOW-level input voltage
FIN HIGH-level input current
FIN LOW-level input current
XIN HIGH-level input current
XIN LOW-level input current
FV, DOP, LD,DOA, FR, OV, OR,
HIGH-level output current
FV, DOP, LD,DOA, FR, OV, OR,
LOW-level output current
DATA to CLK and CLK to LE
setup time
Hold time
fmin1
fmin2
V
FIN
V
XIN
V
IH
V
IL
I
IH1
I
IL1
I
IH2
I
IL2
I
OH
F
IN
=0.5Vp-p , sine wave
F
IN
=0.5Vp-p , sine wave
f
FIN
= 20 to 200MHz sine wave , AC coupling
f
XIN =
1 to 35MHz sine wave , AC coupling
0.5
0.5
V
DD
-0.3
20
1
V
DD
-0.5
V
DD
-0.5
Vp-p
Vp-p
uA
0.3
uA
uA
uA
uA
uA
mA
V
IH
=V
DD
V
IL
=0V
V
IH
=V
DD
V
IL
=0V
V
OH
=V
DD
-0.4V
0.4
100
100
100
100
I
OL
V
OL
=0.4V
0.4
mA
t
su
1
t
su
2
t
H
80
80
80
ns
ns
ns
NIPPON PRECISION CIRCUITS-3
SM5158A
Serial data input timing
DATA
t
SU1
CLK
t
H
t
SU2
LE
Phase detector timing
FR
FV
DOP
DOA
OR
OV
LD
NIPPON PRECISION CIRCUITS-4
SM5158A
DIVIDER DATA SETTING PROCEDURE
CLK
1
DATA
MSB
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
LSB
Control
LE
17
Input data must be MSB first. Final bit(17th
bit) is assigned to the control bit.
Data are written into shift register at the ris-
ing edge of the CLK signal.
When LE is HIGH,data is transferred from
the shift register to either the latch of refer-
ence divider or input divider. Thus data must
be written on the shift register while LE is
remaining LOW.
While all bits of the N latch to are "0", the N
counter will be disabled, DOA, DOP are
floating,and the supply current will be
decreased.
While all bits of the R latch are "O", oscilla-
tor will be disabled.
While all bits of R and N latches are "0", sup-
ply current decreases to 10uA or less.
16 BIT DATA FOR R or N latch
CONTROL
LSB
MSB
Latch select bit ( 1 : R-latch, 0 : N-latch )
NIPPON PRECISION CIRCUITS-5
嵌入式系统
