SM57232457UE0UP
May 31, 2000
Revision History
• May 31, 2000
Added Command Truth Table, Mode Register Table and notes.
Modified waveforms ( Auto Refresh (CBR) cycle and Power Down Mode and Clock Mask).
• March 9, 2000
Modified DC characteristics on page 4.
• January 5, 2000
Modified module length from 133.37mm to 133.35mm.
• February 10, 1999
Modified Intel PC-100 (Rev 1.0) to Intel PC-100 (Rev 1.2).
• October 7, 1998
Defined CAS Latency option.
• August 28, 1998
Modified DC specifications on page 4.
• August 25, 1998
Modified DC & AC specifications on page 6 & 7.
• August 10, 1998
Modified DC specifications on page 6.
• August 6, 1998
Datasheet released.
C
orporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
36 Linford Forum, Rockingham Dr., Linford Wood, Milton Keynes, MK14 6LY, UK • Tel: +44-1908 234030 • Fax: +44-1908-234191
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
1
SM57232457UE0UP
May 31, 2000
256MByte (32M x 72) Synchronous DRAM Module - 32Mx4 based
168-pin DIMM, Registered, ECC
Features
•
•
•
•
•
•
•
Standard
Configuration
Cycle Time
CAS# Latency
Burst Length
Burst Type
No. of Internal
Banks per SDRAM
:
:
:
:
:
:
:
Intel PC-100 (Rev 1.2)
ECC
10ns
3&4/4
1, 2, 4, 8 or Page
Linear/Interleave
4
•
•
•
•
•
•
•
Operating Voltage :
3.3V
Refresh
:
4K/8K
Device Physicals
:
400mil TSOP
Lead Finish
:
Gold
Length x Height
:
133.35mm x 43.18mm
No. of sides
:
Double-sided
Mating Connector (Examples)
Vertical
:
AMP-390052-6
Functional Diagram
REGE
DQMB0~DQMB7
S0#, S2#
RDQMB0~RDQMB7
CKE0#
RAS#
CAS#
WE#
R
E
G
I
S
T
E
R
RS0#, RS2#
RS0#
32Mx20
Block
32Mx20
Block
RS2#
32Mx16
Block
32Mx16
Block
PCK0
PLL
Clock
Buffer
CB0~CB3
DQ0~DQ15
CB4~CB7
DQ32~DQ47
DQ16~DQ31
DQ48~DQ63
DQ0~DQ63, CB0~CB7
CK0
PCK7
PCK1~PCK6
(To all SDRAMs)
Feedback
Notes:
1.
A0~A11, BA0 and BA1 to all SDRAMs through registers.
2.
Register Block comprises of two registers.
3.
Data is terminated using 10Ω series resistors.
4.
REGE, when asserted active high the buffer-register operates in
register mode, when deasserted inactive low the buffer-register
operates in “real-time” buffer mode. REGE has a pull-up of 10KΩ.
5.
CK signals are terminated with series resistors and/or padding
capacitors depending on load per clock.
6.
For RDQMB control see note on page 3.
7.
Each 32Mx16 Block comprises of four 32Mx4 SDRAMs and each
32Mx20 Block comprises of five 32Mx4 SDRAMs.
8.
WP signal has a pull-down of 47KΩ.
SA0~SA2
SCL
WP
A0~A2
SCL
WP
SDA
SDA
SERIAL PD
EEPROM
V
CC
V
SS
Decoupling capacitors
to all devices.
( All specifications of this device are subject to change without notice.)
C
orporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
36 Linford Forum, Rockingham Dr., Linford Wood, Milton Keynes, MK14 6LY, UK • Tel: +44-1908 234030 • Fax: +44-1908-234191
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
2
SM57232457UE0UP
May 31, 2000
Pin Name
A0~A11
A0~A9, A11
BA0, BA1
DQ0~DQ63, CB0~CB7
CK0~CK3
RAS#
CAS#
CKE0, CKE1
DQMB0~DQMB7
S0#, S2#
Row Addresses
Column Addresses
Bank Select Address
Data Inputs/Outputs
Clock Inputs
Row Address Strobes
Column Address Strobes
Clock Enable
DQ Mask Enables
Chip Selects
WE#
REGE
SA0~SA2
SDA
SCL
WP
V
CC
V
SS
NC
Write Enable
Register Enable
Decode Inputs
Serial Data Input/Output
Serial Clock
Serial EEPROM Write Protect
Power Supply
Ground
No Connection
Note:
RDQMs v/s Data I/Os
RDQMB0 controls DQ0~DQ7
RDQMB1 controls DQ8~DQ15,
CB0~CB3
RDQMB2 controls DQ16~DQ23
RDQMB3 controls DQ24~DQ31
RDQMB4 controls DQ32~DQ39
RDQMB5 controls DQ40~DQ47
CB4~CB7
RDQMB6 controls DQ48~DQ55
RDQMB7 controls DQ56~DQ63
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Pin
Designation
V
SS
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
CC
DQ14
DQ15
CB0
CB1
V
SS
NC
NC
V
CC
WE#
DQMB0
DQMB1
S0#
NC
V
SS
A0
A2
A4
A6
A8
A10/AP (Note*)
BA1
V
CC
V
CC
CK0
Pin
No.
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Pin
Designation
V
SS
NC
S2#
DQMB2
DQMB3
NC
V
CC
NC
NC
CB2
CB3
V
SS
DQ16
DQ17
DQ18
DQ19
V
CC
DQ20
NC
NC
CKE1
V
SS
DQ21
DQ22
DQ23
V
SS
DQ24
DQ25
DQ26
DQ27
V
CC
DQ28
DQ29
DQ30
DQ31
V
SS
CK2
NC
WP
SDA
SCL
V
CC
Pin
No.
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
Pin
Designation
V
SS
DQ32
DQ33
DQ34
DQ35
V
CC
DQ36
DQ37
DQ38
DQ39
DQ40
V
SS
DQ41
DQ42
DQ43
DQ44
DQ45
V
CC
DQ46
DQ47
CB4
CB5
V
SS
NC
NC
V
CC
CAS#
DQMB4
DQMB5
NC
RAS#
V
SS
A1
A3
A5
A7
A9
BA0
A11
V
CC
CK1
NC
Pin
No.
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Pin
Designation
V
SS
CKE0
NC
DQMB6
DQMB7
NC
V
CC
NC
NC
CB6
CB7
V
SS
DQ48
DQ49
DQ50
DQ51
V
CC
DQ52
NC
NC
REGE
V
SS
DQ53
DQ54
DQ55
V
SS
DQ56
DQ57
DQ58
DQ59
V
CC
DQ60
DQ61
DQ62
DQ63
V
SS
CK3
NC
SA0
SA1
SA2
V
CC
Note* :
A10/AP initiates Auto-precharge.
C
orporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
36 Linford Forum, Rockingham Dr., Linford Wood, Milton Keynes, MK14 6LY, UK • Tel: +44-1908 234030 • Fax: +44-1908-234191
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
3
SM57232457UE0UP
May 31, 2000
DC Characteristics
Absolute Maximum Ratings
Parameter
Voltage on any pin relative to V
SS
Voltage on supply pins relative to V
SS
Power Dissipation
Operating Temperature
Storage Temperature
Short Circuit Output Current
Recommended DC Operating Conditions
(T
A
= 0 to +65°C)
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min
3.0
0
2.0
-0.3
Typ
3.3
0
-
-
Max
3.6
0
V
CC
+0.3
0.8
Unit
V
V
V
V
Symbol
V
IN,
V
OUT
V
CCQ
P
T
T
opr
T
stg
I
OS
Ratings
- 0.5 to V
CC
+0.5
- 0.5 to 4.5
21
0 to +65
- 55 to +150
50
Unit
V
V
W
°C
°C
mA
C
orporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
36 Linford Forum, Rockingham Dr., Linford Wood, Milton Keynes, MK14 6LY, UK • Tel: +44-1908 234030 • Fax: +44-1908-234191
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
4
SM57232457UE0UP
May 31, 2000
DC Characteristics (cont’d)
Capacitance
(V
CC
= 3.3V±0.3V, T
A
= +25°C)
Parameter
Input Capacitance (All signals except Data & CLKs)
Input Capacitance (CLK0~CLK3)
Input/Output Capacitance (DQ0~DQ63, CB0~CB7)
Notes : Capacitance is sampled per Mil-Std-883.
Symbol
C
I1
C
I2
C
I/O
Max
18
35
17
Unit
pF
pF
pF
(V
CC
= 3.3V±0.3V, V
SS
= 0V, T
A
= 0 to +65 °C)
Parameter
Input Leakage Current*
Output Leakage Current
Output High Voltage
Output Low Voltage
Symbol
I
LI
I
LO
V
OH
V
OL
Test Conditions
0V
≤
V
in
≤
V
CC
+0.3V
0V
≤V
out
≤
V
CC
D
out
= Disable
High I
out
= -4mA
Low I
out
= 4mA
2.4
-
-
0.4
V
V
Min
-10
-10
10ns
Max
10
10
Unit
µA
µA
*Note : Except for REGE (0.33mA) and WP (0.07mA) pins.
C
orporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
36 Linford Forum, Rockingham Dr., Linford Wood, Milton Keynes, MK14 6LY, UK • Tel: +44-1908 234030 • Fax: +44-1908-234191
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
5
