Features ........................................................................................................................................................................................3
Special Function Register (SFR) ................................................................................................................................................ 11
Function Description ...................................................................................................................................................................15
1.
General Features ...............................................................................................................................................................15
Instruction Set ....................................................................................................................................................................18
Program Memory ..............................................................................................................................................22
3.2.
Data Memory ....................................................................................................................................................22
3.2.1.
Data memory - lower 128 byte (00h to 7Fh) ............................................................................................23
3.2.2.
Data memory - higher 128 byte (80h to FFh)...........................................................................................23
3.2.3.
Data memory - Expanded 1024 bytes ($0000 to $03FF).........................................................................24
4.
CPU Engine........................................................................................................................................................................25
B Register .........................................................................................................................................................25
4.3.
Program Status Word........................................................................................................................................26
Data Pointer ......................................................................................................................................................26
4.6.
Data Pointer 1 ...................................................................................................................................................27
4.7.
Internal RAM control register ............................................................................................................................27
4.8.
Interface control register ...................................................................................................................................27
Multiplication Division Unit (MDU)......................................................................................................................................31
6.1.
Operating registers of the MDU ........................................................................................................................31
6.2.
Operation of the MDU .......................................................................................................................................32
6.2.1.
First phase: loading the MDx registers, x = 0~5: .....................................................................................32
6.2.2.
Second phase: executing calculation.......................................................................................................32
6.2.3.
Third phase: reading the result from the MDx registers...........................................................................33
Timer 0 and Timer 1 ...........................................................................................................................................................34
7.1.
Timer/counter mode control register (TMOD)...................................................................................................34
7.2.
Timer/counter control register (TCON) .............................................................................................................35
8.
Timer 2 and Capture/Compare Unit ...................................................................................................................................36
8.1.
Timer 2 function ................................................................................................................................................38
Reload of Timer 2.....................................................................................................................................38
Serial interface 0 and 1 ......................................................................................................................................................41
9.1.
Serial interface 0 ...............................................................................................................................................42
Serial interface 1 ...............................................................................................................................................44
9.2.1.
Mode A .....................................................................................................................................................44
9.2.2.
Mode B .....................................................................................................................................................45
9.3.
Multiprocessor communication of Serial Interface 0 and 1...............................................................................45
Serial interface 0 modes 1 and 3 .............................................................................................................45
9.4.2.
Serial interface 1 modes A and B.............................................................................................................46
9.5.
Clock source for baud rate................................................................................................................................46
Power Management Unit ...........................................................................................................................................54
SPI function ...............................................................................................................................................................62
ISP service program .........................................................................................................................................73
19.2.
Lock Bit (N) .......................................................................................................................................................73
19.3.
Program the ISP Service Program ...................................................................................................................74
19.4.
Initiate ISP Service Program.............................................................................................................................74
DC Characteristics ......................................................................................................................................................................78
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M043
2
Ver.G SM59R04A2 02/2012
SM59R04A2
8-Bit Micro-controller
16KB with ISP Flash
& 1KB RAM embedded
Product List
SM59R04A2L25, SM59R04A2C25
Features
Operating Voltage: 4.5V ~ 5.5V or 2.7V ~ 3.6V
High speed architecture of 1 clock/machine cycle (1T),
runs up to 25MHz
1T/2T modes are software programmable on the fly
Instruction-set compatible with MCS-51
Internal OSC with range 1MHz – 24MHz
16K bytes on-chip flash program memory
External RAM addresses up to 64K bytes.
Standard 12T interface for external RAM access.
256 bytes RAM as standard 8052, plus 1K bytes
on-chip expandable RAM
Dual 16-bit Data Pointers (DPTR0 & DPTR1)
Two serial peripheral interfaces in full duplex mode
