SN54AHCT16541, SN74AHCT16541
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS339H – MARCH 1996 – REVISED JANUARY 2000
D
D
D
D
D
D
D
Members of the Texas Instruments
Widebus
™
Family
EPIC
™
(Enhanced-Performance Implanted
CMOS) Process
Inputs Are TTL-Voltage Compatible
Distributed V
CC
and GND Pins Minimize
High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB
Layout
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
SN54AHCT16541 . . . WD PACKAGE
SN74AHCT16541 . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
description
The ’AHCT16541 devices are noninverting 16-bit
buffers composed of two 8-bit sections with
separate output-enable signals. For either 8-bit
buffer section, the two output-enable (1OE1 and
1OE2 or 2OE1 and 2OE2) inputs must both be low
for the corresponding Y outputs to be active. If
either output-enable input is high, the outputs of
that 8-bit buffer section are in the high-impedance
state.
1OE1
1Y1
1Y2
GND
1Y3
1Y4
V
CC
1Y5
1Y6
GND
1Y7
1Y8
2Y1
2Y2
GND
2Y3
2Y4
V
CC
2Y5
2Y6
GND
2Y7
2Y8
2OE1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE2
1A1
1A2
GND
1A3
1A4
V
CC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
V
CC
2A5
2A6
GND
2A7
2A8
2OE2
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54AHCT16541 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74AHCT16541 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 8-bit buffer/driver)
INPUTS
OE1
L
L
H
X
OE2
L
L
X
H
A
L
H
X
X
OUTPUT
Y
L
H
Z
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
Copyright
©
2000, Texas Instruments Incorporated
•
DALLAS, TEXAS 75265
1
SN54AHCT16541, SN74AHCT16541
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS339H – MARCH 1996 – REVISED JANUARY 2000
logic symbol
†
1OE1
1OE2
2OE1
2OE2
24
25
&
EN2
1
48
&
EN1
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1
1
2
3
5
6
8
9
11
12
1Y1
1Y2
1Y3
1Y4
1Y5
1Y6
1Y7
1Y8
2Y1
2Y2
2Y3
2Y4
2Y5
2Y6
2Y7
2Y8
1
2
13
14
16
17
19
20
22
23
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1OE1
1OE2
1
48
2OE1
2OE2
2
24
25
1A1
47
1Y1
2A1
36
13
2Y1
To Seven Other Channels
To Seven Other Channels
2
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•
DALLAS, TEXAS 75265
SN54AHCT16541, SN74AHCT16541
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS339H – MARCH 1996 – REVISED JANUARY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, V
I
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Output voltage range, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
CC
+ 0.5 V
Input clamp current, I
IK
(V
I
< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Continuous output current, I
O
(V
O
= 0 to V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±25
mA
Continuous current through each V
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±75
mA
Package thermal impedance,
θ
JA
(see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 3)
SN54AHCT16541
MIN
VCC
VIH
VIL
VI
VO
IOH
IOL
∆t/∆v
Supply voltage
High-level input voltage
Low-level input voltage
Input voltage
Output voltage
High-level output current
Low-level output current
Input transition rise or fall rate
0
0
4.5
2
0.8
5.5
VCC
–8
8
20
0
0
MAX
5.5
SN74AHCT16541
MIN
4.5
2
0.8
5.5
VCC
–8
8
20
MAX
5.5
UNIT
V
V
V
V
V
mA
mA
ns/V
TA
Operating free-air temperature
–55
125
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3
SN54AHCT16541, SN74AHCT16541
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS339H – MARCH 1996 – REVISED JANUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VOH
VOL
II
IOZ
ICC
∆I
CC†
Ci
Co
TEST CONDITIONS
IOH = –50
m
A
IOH = –8 mA
IOL = 50
m
A
IOL = 8 mA
VI = VCC or GND
VO = VCC or GND
VI = VCC or GND,
IO = 0
One input at 3.4 V,
Other inputs at VCC or GND
VI = VCC or GND
VO = VCC or GND
VCC
4.5
45V
45V
4.5
0 V to 5.5 V
5.5 V
5.5 V
5.5 V
5V
5V
2
3
TA = 25°C
MIN
TYP
MAX
4.4
3.94
0.1
0.36
±0.1
±0.25
4
1.35
10
4.5
SN54AHCT16541
MIN
4.4
3.8
0.1
0.44
±1*
±2.5
40
1.5
MAX
SN74AHCT16541
MIN
4.4
3.8
0.1
0.44
±1
±2.5
40
1.5
10
MAX
UNIT
V
V
m
A
m
A
m
A
mA
pF
pF
* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
† This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC.
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
±
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tsk(o)
FROM
(INPUT)
A
TO
(OUTPUT)
Y
Y
Y
Y
Y
Y
LOAD
CAPACITANCE
CL = 15 pF
CL = 15 pF
CL = 15 pF
CL = 50 pF
CL = 50 pF
CL = 50 pF
CL = 50 pF
TA = 25°C
MIN
TYP
MAX
5.4**
5.4**
7.7**
7.7**
4.5**
4.5**
6.2
6
7.5
7.5
7
7
8.5**
8.5**
10.4**
10.4**
10.4**
10.4**
9.5
9.5
11.4
11.4
11.4
11.4
1***
SN54AHCT16541
MIN
1**
1**
1**
1**
1**
1**
1
1
1
1
1
1
MAX
10**
10**
12**
12**
12**
12**
11
11
13
13
13
13
SN74AHCT16541
MIN
1
1
1
1
1
1
1
1
1
1
1
1
MAX
9.5
9.5
12
12
12
12
10.5
10.5
13
13
13
13
1
UNIT
ns
ns
ns
ns
ns
ns
ns
OE
OE
A
OE
OE
** On products compliant to MIL-PRF-38535, this parameter is not production tested.
*** On products compliant to MIL-PRF-38535, this parameter does not apply.
noise characteristics, V
CC
= 5 V, C
L
= 50 pF, T
A
= 25°C (see Note 4)
PARAMETER
VOL(P)
VOL(V)
VOH(V)
VIH(D)
Quiet output, maximum dynamic VOL
Quiet output, minimum dynamic VOL
Quiet output, minimum dynamic VOH
High-level dynamic input voltage
2
0.8
SN74AHCT16541
MIN
TYP
0.6
–0.3
4.6
MAX
UNIT
V
V
V
V
V
VIL(D)
Low-level dynamic input voltage
NOTE 4: Characteristics are for surface-mount packages only.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN54AHCT16541, SN74AHCT16541
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS339H – MARCH 1996 – REVISED JANUARY 2000
operating characteristics, V
CC
= 5 V, T
A
= 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
No load,
f = 1 MHz
TYP
12
UNIT
pF
PARAMETER MEASUREMENT INFORMATION
RL = 1 kΩ
S1
VCC
Open
GND
From Output
Under Test
CL
(see Note A)
Test
Point
From Output
Under Test
CL
(see Note A)
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
S1
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
3V
Timing Input
tw
3V
tsu
Data Input
0V
1.5 V
1.5 V
0V
th
3V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
3V
1.5 V
tPZL
50% VCC
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
50% VCC
1.5 V
0V
tPLZ
≈V
CC
VOL + 0.3 V
VOL
tPHZ
VOH – 0.3 V
VOH
≈0
V
Input
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
Input
tPLH
In-Phase
Output
tPHL
Out-of-Phase
Output
1.5 V
1.5 V
0V
tPHL
50% VCC
VOH
50% VCC
VOL
tPLH
50% VCC
VOH
50% VCC
VOL
Output
Control
Output
Waveform 1
S1 at VCC
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤
1 MHz, ZO = 50
Ω,
tr
≤
3 ns, tf
≤
3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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5
