SN54HC367, SN74HC367
HEX BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SCLS309B – JANUARY 1996 – REVISED MAY 1997
D
D
D
High-Current 3-State Outputs Drive Bus
Lines, Buffer Memory Address Registers,
or Drive up to 15 LSTTL Loads
True Outputs
Package Options Include Plastic
Small-Outline (D) and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J)
300-mil DIPs
SN54HC367 . . . J OR W PACKAGE
SN74HC367 . . . D OR N PACKAGE
(TOP VIEW)
description
These hex buffers and line drivers are designed
specifically to improve both the performance and
density of 3-state memory address drivers, clock
drivers, and bus-oriented receivers and
transmitters. The ’HC367 are organized as dual
4-line and 2-line buffers/drivers with active-low
output-enable (1OE and 2OE) inputs. When OE is
low, the device passes noninverted data from the
A inputs to the Y outputs. When OE is high, the
outputs are in the high-impedance state.
The SN54HC367 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74HC367 is characterized for
operation from –40°C to 85°C.
1OE
1A1
1Y1
1A2
1Y2
1A3
1Y3
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
2OE
2A2
2Y2
2A1
2Y1
1A4
1Y4
SN54HC367 . . . FK PACKAGE
(TOP VIEW)
1A1
1OE
NC
V
CC
2OE
1Y1
1A2
NC
1Y2
1A3
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
2A2
2Y2
NC
2A1
2Y1
NC – No internal connection
FUNCTION TABLE
(each buffer/driver)
INPUTS
OE
H
L
L
A
X
H
L
OUTPUT
Y
Z
H
L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
©
1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1Y3
GND
NC
1Y4
1A4
1
SN54HC367, SN74HC367
HEX BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SCLS309B – JANUARY 1996 – REVISED MAY 1997
logic symbol
†
1
1OE
2
4
6
10
EN
3
5
7
9
1A1
1A2
1A3
1A4
1Y1
1Y2
1Y3
1Y4
15
2OE
12
14
EN
11
13
2A1
2A2
2Y1
2Y2
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, N, and W packages.
logic diagram (positive logic)
1OE
1
2OE
15
1A1
2
3
1Y1
2A1
12
11
2Y1
To Three Other Channels
Pin numbers shown are for the D, J, N, and W packages.
To One Other Channel
absolute maximum ratings over operating free-air temperature range
‡
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Continuous output current, I
O
(V
O
= 0 to V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±35
mA
Continuous current through V
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±70
mA
Package thermal impedance,
θ
JA
(see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
2
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DALLAS, TEXAS 75265
SN54HC367, SN74HC367
HEX BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SCLS309B – JANUARY 1996 – REVISED MAY 1997
recommended operating conditions
SN54HC367
MIN
VCC
VIH
Supply voltage
High-level input voltage
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
VCC = 2 V
VIL
VI
VO
tt
TA
Low-level input voltage
Input voltage
Output voltage
Input transition (rise and fall) time
Operating free-air temperature
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
VCC = 4.5 V
VCC = 6 V
2
1.5
3.15
4.2
0
0
0
0
0
0
0
0
–55
0.5
1.35
1.8
VCC
VCC
1000
500
400
125
NOM
5
MAX
6
SN74HC367
MIN
2
1.5
3.15
4.2
0
0
0
0
0
0
0
0
–40
0.5
1.35
1.8
VCC
VCC
1000
500
400
85
°C
ns
V
V
V
V
NOM
5
MAX
6
UNIT
V
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
2V
IOH = –20
µA
VOH
VI = VIH or VIL
IOH = –6 mA
IOH = –7.8 mA
IOL = 20
µA
VOL
VI = VIH or VIL
IOL = 6 mA
IOL = 7.8 mA
II
IOZ
ICC
Ci
VI = VCC or 0
VO = VCC or 0
VI = VCC or 0,
IO = 0
4.5 V
6V
4.5 V
6V
2V
4.5 V
6V
4.5 V
6V
6V
6V
6V
2 V to 6 V
3
TA = 25°C
MIN
TYP
MAX
1.9
4.4
5.9
3.98
5.48
1.998
4.499
5.999
4.3
5.8
0.002
0.001
0.001
0.17
0.15
±0.1
±0.01
0.1
0.1
0.1
0.26
0.26
±100
±0.5
8
10
SN54HC367
MIN
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±1000
±10
160
10
MAX
SN74HC367
MIN
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±1000
±5
80
10
nA
µA
µA
pF
V
V
MAX
UNIT
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SN54HC367, SN74HC367
HEX BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SCLS309B – JANUARY 1996 – REVISED MAY 1997
switching characteristics over recommended operating free-air temperature range, C
L
= 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
2V
tpd
A
Y
4.5 V
6V
2V
ten
OE
Y
4.5 V
6V
2V
tdis
OE
Y
4.5 V
6V
2V
tt
Any
4.5 V
6V
TA = 25°C
MIN
TYP
MAX
50
12
10
100
26
21
50
21
19
28
8
6
95
19
16
190
38
32
175
35
30
60
12
10
SN54HC367
MIN
MAX
145
29
25
285
57
48
265
53
45
90
18
15
SN74HC367
MIN
MAX
120
24
20
238
48
41
240
48
41
75
15
13
ns
ns
ns
ns
UNIT
switching characteristics over recommended operating free-air temperature range, C
L
= 150 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
2V
tpd
A
Y
4.5 V
6V
2V
ten
OE
Y
4.5 V
6V
2V
tt
Any
4.5 V
6V
TA = 25°C
MIN
TYP
MAX
70
17
14
140
30
28
45
17
13
120
24
20
230
46
39
210
42
36
SN54HC367
MIN
MAX
180
36
31
345
69
59
315
63
53
SN74HC367
MIN
MAX
150
30
25
285
57
48
265
53
45
ns
ns
ns
UNIT
operating characteristics, T
A
= 25°C
PARAMETER
Cpd
Power dissipation capacitance per buffer/driver
TEST CONDITIONS
No load
TYP
35
UNIT
pF
4
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DALLAS, TEXAS 75265
SN54HC367, SN74HC367
HEX BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SCLS309B – JANUARY 1996 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
VCC
PARAMETER
Test
Point
S1
RL
ten
tPZH
tPZL
tPHZ
tPLZ
––
50 pF
or
150 pF
1 kΩ
RL
1 kΩ
CL
50 pF
or
150 pF
50 pF
S1
Open
Closed
Open
Closed
Open
S2
Closed
Open
Closed
Open
Open
From Output
Under Test
CL
(see Note A)
S2
tdis
tpd or tt
LOAD CIRCUIT
VCC
Input
50%
tPLH
In-Phase
Output
50%
10%
tPHL
Out-of-Phase
Output
90%
50%
10%
tf
90%
tr
tPLH
50%
10%
90%
tr
VOH
VOL
50%
0V
tPHL
90%
VOH
50%
10% V
OL
tf
Output
Control
(Low-Level
Enabling)
tPZL
Output
Waveform 1
(See Note B)
tPZH
VCC
50%
50%
0V
tPLZ
≈
VCC
50%
10%
≈
VCC
VOL
VOH
≈
0V
tPHZ
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
VCC
50%
10% 0 V
tf
Input
50%
10%
90%
90%
Output
Waveform 2
(See Note B)
50%
90%
tr
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR
≤
1 MHz, ZO = 50
Ω,
tr = 6 ns, tf = 6 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLH and tPHL are the same as tpd.
F. tPLZ and tPHZ are the same as tdis.
G. tPZL and tPZH are the same as ten.
Figure 1. Load Circuit and Voltage Waveforms
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