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SN74ALVCH16721
3.3-V 20-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES052D – JULY 1995 – REVISED FEBRUARY 1999
D
Member of the Texas Instruments
D
D
D
D
D
Widebus
Family
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
description
This 20-bit flip-flop is designed specifically for
1.65-V to 3.6-V V
CC
operation.
The 20 flip-flops of the SN74ALVCH16721 are
edge-triggered D-type flip-flops with qualified
clock storage. On the positive transition of the
clock (CLK) input, the device provides true data at
the Q outputs if the clock-enable (CLKEN) input is
low. If CLKEN is high, no data is stored.
A buffered output-enable (OE) input places the
20 outputs in either a normal logic state (high or
low) or the high-impedance state. In the
high-impedance state, the outputs neither load
nor drive the bus lines significantly. The
high-impedance state and increased drive
provide the capability to drive bus lines without
need for interface or pullup components. OE does
not affect the internal operation of the flip-flops.
Old data can be retained or new data can be
entered while the outputs are in the
high-impedance state.
OE
Q1
Q2
GND
Q3
Q4
V
CC
Q5
Q6
Q7
GND
Q8
Q9
Q10
Q11
Q12
Q13
GND
Q14
Q15
Q16
V
CC
Q17
Q18
GND
Q19
Q20
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
CLK
D1
D2
GND
D3
D4
V
CC
D5
D6
D7
GND
D8
D9
D10
D11
D12
D13
GND
D14
D15
D16
V
CC
D17
D18
GND
D19
D20
CLKEN
NC – No internal connection
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16721 is characterized for operation from –40°C to 85°C.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
1999, Texas Instruments Incorporated
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3–263
SN74ALVCH16721
3.3-V 20-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES052D – JULY 1995 – REVISED FEBRUARY 1999
FUNCTION TABLE
(each flip-flop)
INPUTS
OE
L
L
L
L
H
CLKEN
H
L
L
L
X
CLK
X
↑
↑
L or H
X
D
X
H
L
X
X
OUTPUT
Q
Q0
H
L
Q0
Z
logic diagram (positive logic)
1
OE
56
CLK
29
CLKEN
55
1D
CE
C1
D1
2
Q1
To 19 Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, V
I
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Output voltage range, V
O
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
CC
+ 0.5 V
Input clamp current, I
IK
(V
I
< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, I
OK
(V
O
< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, I
O
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±50
mA
Continuous current through each V
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±100
mA
Package thermal impedance,
θ
JA
(see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
3–264
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN74ALVCH16721
3.3-V 20-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES052D – JULY 1995 – REVISED FEBRUARY 1999
recommended operating conditions (see Note 4)
MIN
VCC
VIH
Supply voltage
High-level input voltage
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 1.65 V to 1.95 V
VIL
VI
VO
Low-level input voltage
Input voltage
Output voltage
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
0
0
1.65
0.65
×
VCC
1.7
2
0.35
×
VCC
0.7
0.8
VCC
VCC
–4
–12
–12
–24
4
12
12
24
10
ns/V
mA
mA
V
V
V
V
MAX
3.6
UNIT
V
IOH
High-level output current
IOL
Low-level output current
∆t/∆v
Input transition rise or fall rate
TA
Operating free-air temperature
–40
85
°C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3–265
SN74ALVCH16721
3.3-V 20-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES052D – JULY 1995 – REVISED FEBRUARY 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
IOH = –100
µA
IOH = –4 mA
IOH = –6 mA
VOH
IOH = –12 mA
IOH = –24 mA
IOL = 100
µA
IOL = 4 mA
IOL = 6 mA
IOL = 12 mA
IOL = 24 mA
VI = VCC or GND
VI = 0.58 V
VI = 1.07 V
II(hold)
VI = 0.7 V
VI = 1.7 V
VI = 0.8 V
VI = 2 V
IOZ
ICC
∆I
CC
Ci
Co
Control inputs
Data inputs
Outputs
VI = 0 to 3.6 V‡
VO = VCC or GND
VI = VCC or GND,
One input at VCC – 0.6 V,
VI = VCC or GND
IO = 0
Other inputs at VCC or GND
TEST CONDITIONS
VCC
1.65 V to 3.6 V
1.65 V
2.3 V
2.3 V
2.7 V
3V
3V
1.65 V to 3.6 V
1.65 V
2.3 V
2.3 V
2.7 V
3V
3.6 V
1.65 V
1.65 V
2.3 V
2.3 V
3V
3V
3.6 V
3.6 V
3.6 V
3 V to 3.6 V
3.3 V
3.5
6
25
–25
45
–45
75
–75
±500
±10
40
750
µA
µA
µA
pF
µA
MIN
TYP†
MAX
UNIT
VCC–0.2
1.2
2
1.7
2.2
2.4
2
0.2
0.45
0.4
0.7
0.4
0.55
±5
µA
V
V
VOL
II
VO = VCC or GND
3.3 V
7
pF
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 1 through 3)
VCC = 1.8 V
MIN
fclock
tw
tsu
th
Clock frequency
Pulse duration, CLK high or low
Setup time
Hold time
Data before CLK↑
CLKEN before CLK↑
Data after CLK↑
CLKEN after CLK↑
§
§
§
§
§
MAX
§
VCC = 2.5 V
±
0.2 V
MIN
3.3
4
3.4
0
0
MAX
150
3.3
3.6
3.1
0
0
VCC = 2.7 V
MIN
MAX
150
3.3
3.1
2.7
0
0
VCC = 3.3 V
±
0.3 V
MIN
MAX
150
MHz
ns
ns
ns
UNIT
§ This information was not available at the time of publication.
3–266
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•
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