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SN74LVT16835
3.3-V ABT 18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCBS309D – MARCH 1994 – REVISED NOVEMBER 1996
D
D
D
D
D
D
D
D
D
D
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low-Static Power
Dissipation
Member of the Texas Instruments
Widebus
™
Family
Supports Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
3.3-V V
CC
)
Supports Unregulated Battery Operation
Down to 2.7 V
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 3.3 V, T
A
= 25°C
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Supports Live Insertion
Distributed V
CC
and GND Pin Configuration
Minimizes High-Speed Switching Noise
Flow-Through Architecture Optimizes
PCB Layout
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages Using 25-mil
Center-to-Center Spacings
DGG OR DL PACKAGE
(TOP VIEW)
description
The SN74LVT16835 is an 18-bit universal bus
driver designed for low-voltage (3.3-V) V
CC
operation, but with the capability to provide a TTL
interface to a 5-V system environment.
NC
NC
Y1
GND
Y2
Y3
V
CC
Y4
Y5
Y6
GND
Y7
Y8
Y9
Y10
Y11
Y12
GND
Y13
Y14
Y15
V
CC
Y16
Y17
GND
Y18
OE
LE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
NC
A1
GND
A2
A3
V
CC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
V
CC
A16
A17
GND
A18
CLK
GND
NC – No internal connection
Data flow from A to Y is controlled by the
output-enable (OE) input. This device operates in
the transparent mode when the latch-enable (LE)
input is high. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the
A-bus data is stored in the latch/flip-flop on the low-to-high transition of the clock. When OE is high, the outputs
are in the high-impedance state.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74LVT16835 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG) packages,
which provide twice the input/output (I/O) pins and functionality of standard small-outline packages in the same
printed circuit board area.
The SN74LVT16835 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
©
1996, Texas Instruments Incorporated
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
1
SN74LVT16835
3.3-V ABT 18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCBS309D – MARCH 1994 – REVISED NOVEMBER 1996
FUNCTION TABLE
INPUTS
OE
H
L
L
L
L
L
L
LE
X
H
H
L
L
L
L
CLK
X
X
X
↑
↑
H
L
A
X
L
H
L
H
X
X
OUTPUT
Y
Z
L
H
L
H
Y0†
Y0‡
† Output level before the indicated steady-state
input conditions were established, provided
that CLK was high before LE went low
‡ Output level before the indicated steady-state
input conditions were established
logic symbol
§
27
OE
CLK
LE
30
28
EN1
2C3
C3
G2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
3
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
26
1
1
3D
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
§ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN74LVT16835
3.3-V ABT 18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCBS309D – MARCH 1994 – REVISED NOVEMBER 1996
logic diagram (positive logic)
OE
27
CLK
30
LE
28
A1
54
1D
C1
CLK
3
Y1
To 17 Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, V
I
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Voltage range applied to any output in the high state or power-off state, V
O
(see Note 1) . . . . –0.5 V to 7 V
Current into any output in the low state, I
O
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Current into any output in the high state, I
O
(see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 mA
Input clamp current, I
IK
(V
I
< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, I
OK
(V
O
< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Maximum power dissipation at T
A
= 55°C (in still air) (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . 1 W
DL package . . . . . . . . . . . . . . . . . . . 1.4 W
Operating free-air temperature range, T
A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the
Package Thermal Considerations
application note in the
ABT Advanced BiCMOS Technology Data
Book.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3
SN74LVT16835
3.3-V ABT 18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCBS309D – MARCH 1994 – REVISED NOVEMBER 1996
recommended operating conditions (see Note 4)
MIN
VCC
VIH
VIL
VI
IOH
IOL
∆t/∆v
Supply voltage
High-level input voltage
Low-level input voltage
Input voltage
High-level output current
Low-level output current
Input transition rise or fall rate
Outputs enabled
–40
2.7
2
0.8
5.5
–32
64
10
85
MAX
3.6
UNIT
V
V
V
V
mA
mA
ns/V
°C
TA
Operating free-air temperature
NOTE 4: Unused control inputs must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
VCC = 2.7 V,
VCC = 2.7 V to 3.6 V,
VCC = 2.7 V,
VCC = 3 V
VCC = 2 7 V
2.7
VOL
VCC = 3 V
VCC = 0 or 3.6 V,
VCC = 3.6 V,
VCC = 3.6 V
VCC = 0,
A inputs
VCC = 3 V
VCC = 3.6 V,
VCC = 3.6 V,
VCC = 3.6 V,
36V
VI = VCC or GND
TEST CONDITIONS
II = –18 mA
IOH = –100
µA
IOH = –8 mA
IOH = –32 mA
IOL = 100
µA
IOL = 24 mA
IOL = 16 mA
IOL = 32 mA
IOL = 64 mA
VI = 5.5 V
VI = VCC or GND
VI = VCC
VI = 5.5 V
VI = 0
Ioff
II(hold)
I(h ld)
IOZH
IOZL
ICC
VI or VO = 0 to 4.5 V
VI = 0.8 V
VI = 2 V
VO = 3 V
VO = 0.5 V
Outputs high
IO = 0
0,
Outputs low
Outputs disabled
75
–75
1
–1
0.12
5
0.12
0.2
3.5
4.5
mA
pF
pF
mA
MIN
TYP†
MAX
–1.2
VCC–0.2
2.4
2
0.2
0.5
0.4
0.5
0.55
10
±1
1
20
–5
±100
µA
µA
µA
µA
µ
µA
V
UNIT
V
V
Control inputs
II
A inputs
∆I
CC‡
Ci
Control inputs
Data pins
VCC = 3 V to 3.6 V,
One input at VCC – 0.6 V,
Other inputs at VCC or GND
VI = 3 V or 0
Co
VO = 3 V or 0
11
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
4
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