SN55182, SN75182
DUAL DIFFERENTIAL LINE RECEIVERS
SLLS092D – OCTOBER 1972 – REVISED APRIL 1998
D
D
D
D
D
D
D
D
D
D
D
Single 5-V Supply
Differential Line Operation
Dual Channels
TTL Compatibility
±15-V
Common-Mode Input Voltage Range
±15-V
Differential Input Voltage Range
Individual Channel Strobes
Built-In Optional Line-Termination Resistor
Individual Frequency Response Controls
Designed for Use With Dual Differential
Drivers SN55183 and SN75183
Designed to Be Interchangeable With
National Semiconductor DS7820A and
DS8820A
SN55182 . . . J OR W PACKAGE
SN75182 . . . N PACKAGE
(TOP VIEW)
1IN–
1R
T
1IN+
1STRB
1RTC
1OUT
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
2IN–
2R
T
2IN+
2STRB
2RTC
2OUT
SN55182 . . . FK PACKAGE
(TOP VIEW)
1R
T
description
The SN55182 and SN75182 dual differential line
receivers are designed to sense small differential
signals in the presence of large common-mode
noise. These devices give TTL-compatible output
signals as a function of the polarity of the
differential input voltage. The frequency response
of each channel can be easily controlled by a
single external capacitor to provide immunity to
differential noise spikes. The output goes to a high
level when the inputs are open circuited. A strobe
input (STRB) is provided that, when in the low
level, disables the receiver and forces the output
to a high level.
1IN+
NC
1STRB
NC
1RTC
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
1IN+
NC
V
CC
2IN–
2R
T
NC
2IN+
NC
2STRB
NC – No internal connection
THE SN55182 IS NOT RECOMMENDED
FOR NEW DESIGNS
The receiver is of monolithic single-chip construction, and both halves of the dual circuits use common
power-supply and ground terminals.
The SN55182 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN75182 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
STRB
L
H
H
VID
X
H
L
OUTPUT
OUT
H
H
L
H = VI
≥
VIH min or VID more
positive than VTH max
L = VI
≤
VIL max or VID more
negative than VTL max
X = irrelevant
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
©
1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
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1OUT
GND
NC
2OUT
2RTC
1
SN55182, SN75182
DUAL DIFFERENTIAL LINE RECEIVERS
SLLS092D – OCTOBER 1972 – REVISED APRIL 1998
logic symbol
†
1IN+
1IN–
1RT
1STRB
1RTC
2IN+
2IN–
2RT
2STRB
2RTC
3
1
2
4
5
11
13
12
10
9
8
2OUT
RESP
RT
6
1OUT
&
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the J, N, and W packages.
logic diagram (positive logic)
1IN+
1IN–
1RT
1RTC
1STRB
2IN+
2IN–
2RT
2RTC
2STRB
3
1
2
5
4
11
13
12
9
10
8
2OUT
6
1OUT
Pin numbers shown are for the J, N, and W packages.
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN55182, SN75182
DUAL DIFFERENTIAL LINE RECEIVERS
SLLS092D – OCTOBER 1972 – REVISED APRIL 1998
schematic (each receiver)
RTC
5, 9
14
VCC
167
Ω
5 kΩ
3 kΩ
1.5 kΩ
4.15 kΩ
5 kΩ
320
Ω
6, 8
OUT
1.5 kΩ
3, 11
IN+
170
Ω
2, 12
5 kΩ
1 kΩ
1 kΩ
167
Ω
1 kΩ
750
Ω
RT
7
GND
167
Ω
ÁÁÁ
IN–
1, 13
4, 10
5 kΩ
STRB
Resistor values shown are nominal.
Pin numbers shown are for the J, N, and W packages.
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3
SN55182, SN75182
DUAL DIFFERENTIAL LINE RECEIVERS
SLLS092D – OCTOBER 1972 – REVISED APRIL 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage, V
CC
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V
Common-mode input voltage, V
IC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
V
Differential input voltage, V
ID
(see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
V
Strobe input voltage, V
I(STRB)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V
Output sink current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J or W package . . . . . . . . . . . . . . . . 300°C
Case temperature for 60 seconds, T
c
: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to network ground terminal.
2. Differential voltage values are at the noninverting terminal with respect to the inverting terminal.
DISSIPATION RATING TABLE
PACKAGE
FK‡
J‡
N
W‡
TA
≤
25°C
POWER RATING
1375 mW
1375 mW
1150 mW
1000 mW
DERATING FACTOR
ABOVE TA = 25°C
11.0 mW/°C
11.0 mW/°C
9.2 mW/°C
8.0 mW/°C
TA = 70°C
POWER RATING
880 mW
880 mW
736 mW
640 mW
TA = 125°C
POWER RATING
275 mW
275 mW
–
200 mW
‡ In the FK, J, and W packages, SN55182 chips are alloy mounted.
recommended operating conditions
SN55182
MIN
Supply voltage, VCC
Common-mode input voltage, VIC
High-level strobe input voltage, VIH(STRB)
Low-level strobe input voltage, VIL(STRB)
High-level output current, IOH
Low-level output current, IOL
Operating free-air temperature, TA
–55
2.1
0
4.5
NOM
5
MAX
5.5
±15
5.5
0.9
–400
16
125
0
2.1
0
MIN
4.5
SN75182
NOM
5
MAX
5.5
±15
5.5
0.9
–400
16
70
UNIT
V
V
V
V
µA
mA
°C
4
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DALLAS, TEXAS 75265
SN55182, SN75182
DUAL DIFFERENTIAL LINE RECEIVERS
SLLS092D – OCTOBER 1972 – REVISED APRIL 1998
electrical characteristics over recommended ranges of V
CC
, V
IC
, and operating free-air
temperature (unless otherwise noted)
PARAMETER
VIT
IT+
VIT
IT–
VOH
VOL
Positive-going
Positive going input threshold voltage
Negative going input threshold voltage
Negative-going
TEST CONDITIONS†
VO = 2.5 V,
,
IOH = –400
µA
VO = 0.4 V,
,
IOL = 16 mA
VIC = –3 V to 3 V
VIC = –15 V to 15 V
VIC = –3 V to 3 V
VIC = –15 V to 15 V
2.5
25
2.5
25
4.2
42
4.2
42
0 25
0.25
3
0
–3
5
–1
–7
–1
3.6
1.8
TA = 25°C
VCC = 5.5 V,
VIC = 15 V,
VIC = 0,
VIC = –15 V,
† Unless otherwise noted, V(STRB)
≥
2.1 V or open.
‡ All typical values are at VCC = 5 V, VIC = 0, and TA = 25°C.
120
VO = 0
VID = –1 V
VID = –0.5 V
VID = –1 V
–2.8
5
2.5
170
–4.5
4.2
6.8
9.4
250
–6.7
6
10.2
14
mA
MIN
TYP‡
MAX
0.5
1
–0.5
–1
5.5
55
V
5.5
55
04
0.4
4.2
–0.5
–4.2
7
–1.4
–9.8
5
–1.4
µA
mA
kΩ
Ω
mA
mA
V
UNIT
V
V
High level output voltage
High-level
Low level output voltage
Low-level
VID = 1 V V(STRB) = 2 1 V IOH = –400
µA
V,
2.1 V,
400
VID = –1 V V(STRB) = 0 4 V IOH = –400
µA
1 V,
0.4 V,
400
VID = –1 V V(STRB) = 2 1 V IOL = 16 mA
1 V,
2.1 V,
VIC = 15 V
VIC = 0
VIC = –15 V
VIC = 15 V
Inverting input
II
Input current
Noninverting input
IIH(STRB)
IIL(STRB)
ri
High-level strobe input current
Low-level strobe input current
Input resistance
Inverting input
Noninverting input
VIC = 0
VIC = –15 V
V(STRB) = 5.5 V
V(STRB) = 0
Line-terminating resistance
IOS
ICC
Short-circuit output current
Supply current (average per receiver)
switching characteristics, V
CC
= 5 V, T
A
= 25°C
PARAMETER
tPLH(D)
tPHL(D)
tPLH(S)
tPHL(S)
Propagation delay time,
low- to high-level output from differential input
Propagation delay time,
high- to low-level output from differential input
Propagation delay time,
low- to high-level output from STRB input
Propagation delay time,
high- to low-level output from STRB input
TEST CONDITIONS
RL = 400
Ω,
RL = 400
Ω,
RL = 400
Ω,
RL = 400
Ω,
CL = 15 pF,
CL = 15 pF,
CL = 15 pF,
CL = 15 pF,
see Figure 1
see Figure 1
see Figure 1
see Figure 1
MIN
TYP
18
31
9
15
MAX
40
45
30
25
UNIT
ns
ns
ns
ns
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5
