SP5668
2.7GHz 3-Wire Bus Controlled Synthesiser
Preliminary Information
DS4538
ISSUE 1.6
January 1997
The SP5668 is a single chip frequency synthesiser
designed for tuning systems up to 2.7GHz.
The RF preamplifer contains a divide by two prescaler
which can be disabled for applications up to 2GHz so enabling
a step size equal to the comparison frequency up to 2GHz and
twice the comparison frequency up to 2.7GHz.
Comparison frequencies are obtained either from a crystal
controlled on–chip oscillator or from an external source.
The device contains three switching ports, P0 – P2,
together with an ’in–lock’ flag output. Various test modes
including varactor disable and charge pump disable are also
included.
Ordering Information
SP5668/KG/MP1S (Tubes)
SP5668/KG/MP1T Tape and Reel)
Features
• Complete 2.7GHz single chip system
• Optimised for low phase noise
• Selectable divide by two prescaler
• Selectable reference division ratio
• Charge pump disable
• Varactor line disable
• ‘In–lock’ flag
• Two selectable charge pump currents
• Three switching ports
• Reference frequency output
• ESD protection (Normal ESD handling procedures
should be observed)
CHARGE PUMP
CAP Q1
CRYSTAL Q2
ENABLE
DATA
CLOCK
PORT P2
PORT P1/OC
DRIVE
V
EE
RF INPUT
RF INPUT
V
CC
LOCK
REF
PORT P0/OC
MP16
Figure 1 - Pin connections - top view
Applications
• SAT, TV, VCR and Cable tuning systems
• Communications systems
SP5668
Preliminary Information
Fref
PROGRAMMABLE
DIVIDER
13
INPUTS
14
RF
÷
2/1
÷
16/17
13 BIT
COUNT
Fpd
PHASE
COMP
Fcomp
REFERENCE
DIVIDER
See Table 1
OSC
REF
CRYSTAL
Q1
CRYSTAL
Q2
1
CHARGE
PUMP
DRIVE
DE
4 BIT
COUNT
CHARGE
PUMP
OS
CO
1 BIT
LATCH
3 BIT LATCH
(R0,R1,R2)
1 BIT
LATCH
16
18 BIT LATCH
DISABLE
ENABLE 4
CLOCK
DATA
5
6
DATA
INTERFACE
3 BIT
LATCH AND
PORT
INTERFACE
1 BIT
LATCH
FLOCK
P2 P1 P0
LOCK
Figure 2 - SP5668 block diagram
Electrical Characteristics
T
AMB
= 120°C to +80°C, V
CC
= +4.5 to +5.5V. Reference frequency = 4MHz. These characteristics are guaranteed by
either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless
otherwise stated.
Characteristic
Pin
Min
Supply current, Icc
RF input voltage
13, 14
13,14
RF input impedance
Data, Clock, Enable
Input high voltage
Input low voltage
Input high current
Input low current
Hysteresis
Clock Rate
12
13, 14
40
40
13, 14
4,5,6
3
0
V
CC
0.7
10
-10
400
6
500
V
V
µA
µA
mV
kHz
100
Value
Typ
65
58
Max
81
72
300
300
300
mA
mA
mV
rms
mV
rms
mV
rms
Vcc = 5V Prescaler enabled, PE = 1
Vcc = 5V Prescaler disabled, PE = 0
100MHz Prescaler enabled, PE = 1
See Fig. 5b.
300MHz - 2.7GHz Prescaler enabled,
PE = 1, See Fig. 5b.
100MHz to 2.0GHz Prescaler
disabled, PE = 0, See Fig. 5a
See Fig. 4.
Units
Conditions
Input voltage = V
CC
Input voltage = V
EE
2
SP5668
Electrical Characteristics (continued)
T
AMB
= 120°C to +80°C, V
CC
= +4.5 to +5.5V. Reference frequency = 4MHz. These characteristics are guaranteed by
either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless
otherwise stated.
Characteristic
Pin
Min
Bus timing
Data set up , t
SU
Data hold, t
HD
Enable set up, t
ES
Enable hold , t
EH
Clock to enable, t
CE
Charge pump output
Current
Charge pump output
leakage
Drive output current
Drive output saturation
Voltage when disabled
External reference input
frequency
External reference input
amplitude
Crystal frequency
Recommended crystal
Series resistance
4, 5, 6
300
600
300
600
300
1
1
16
16
3
3
3
1
350
2
200
4
10
20
500
12
200
±10
nA
mA
mV
MHz
mVp-p
MHz
Ω
ns
ns
ns
ns
ns
See Fig. 3
See Fig. 3
See Fig. 3
See Fig. 3
See Fig. 3
See Table 3, V
pin1
=2V
V
pin1
= 2V
V
PIN16
= 0.7V
OS = 1
AC coupled sinewave
AC coupled sinewave
Value
Typ
Max
Units
Conditions
Reference oscillator bias
current
REF output voltage*
Phase detector comparison
frequency
Equivalent phase noise at
phase detector
RF division ratio
Reference division ratio
Output ports P0-P2
Sink current
Leakage current
Lock output
Sink current
Leakage current
3
10
200
350
4
µA
mVp-p
MHz
dBc/Hz
Applies to 4MHz crystal only.
"Parallel resonant" crystal. Figure
quoted is under all conditions
including start up.
See Fig. 11
AC coupled, 4MHz reference
frequency, See Fig.
See **Note
PE = 0, Prescaler disabled
PE = 1, Prescaler enabled
See Table 1
240
480
7-9
10
131071
262142
10
1
10
mA
µA
mA
µA
V
PORT
= 0.7V
V
PORT
= 13.2V
V
PIN10
= 0.7V,
'out of lock'
'in lock'
* REF output should be connected to V
CC
if unused
** Note:
1. -148dBc/Hz @ 1KHz offset with 1MHz comparison frequency measured at the phase comparator.
2. When external reference is used, a high signal level is required for low phase noise.
3
SP5668
Preliminary Information
Absolute Maximum Ratings
All voltages are referred to V
EE
at 0V
Charateristics
Pin
Supply voltage, V
CC
12
RF input voltage
13, 14
RF input offset
13, 14
Port output voltage
7-9
7-9
Total port current
REFoutput DC offset
Lock output DC offset
Lock output current
Charge pump DC offset
Drive DC offset
Crystal oscillator DC offset
Data, Clock & inputs
Storage temperature
Junction temperature
MP16 Thermal resistance
Chip to ambient
Chip to case
Power consumption
at V
CC
= 5.5V
ESD protection
7-9
10
11
11
1
16
2, 3
4,5,6
Min
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-55
Max
7
2.5
V
CC
+0.3
14
6
50
V
CC
+0.3
V
CC
+0.3
10
V
CC
+0.3
V
CC
+0.3
V
CC
+0.3
V
CC
+0.3
+150
+150
111
41
407
ALL
2
Units
V
Vp-p
V
V
V
mA
V
V
mA
V
V
V
V
°C
°C
°C/W
°C/W
mV
kV
Conditions
Port in off state
Port in on state
All ports off, prescaler enabled
MIL-STD 883 TM3015
Functional Description
The SP5668 contains all the elements necessary, with the
exception of a frequency reference, loop filter and external
high voltage transistor, to control a varicap tuned local oscil-
lator, so forming a complete PLL frequency synthesised
source. The device allows for operation with a high compari-
son frequency and is fabricated in high speed logic, which
enables the generation of a loop with good phase noise
performance. The RF preamplifier contains a selectable di-
vide by two for operation above 2.0GHz. Up to 2GHz the RF
input interfaces directly with the programmable divider, so
eliminating degradation in phase noise due to the prescaler
action. The block diagram is shown in Fig.2.
The SP5668 is controlled by a standard 3–wire bus com-
prising data, clock and enable inputs. The programming word
contains 27 bits. P0 - P2 are used for port selection, 2
17
- 2
0
set
the programmable divider ratio R2 - R0 select the reference
division ratio (Table1). C0 sets the charge pump current
(Table 3) and the remaining two bits T0, OS access test modes
and disable the varactor drive (Table 2).The programming
format is shown in Fig. 3.
The clock input is disabled by an enable low signal, data is
therefore only clocked into the internal shift registers during an
enable high and is loaded into the controlling buffers by an
enable high to low transition. This load is also synchronised
with the programmable divider so giving smooth fine tuning.
The RF signal is fed to an internal preamplifier, which
provides gain and reverse isolation from the divider signals.
The output of the preamplifier is fed to the
÷
2/1 selectable
prescaler and then to the 17 bit fully programmable divider,
which is of MN+A architecture. The M counter is 13 bit and the
A counter 4. If bit PE is set to a 0 the prescaler is disabled;
the control function PE cannot be used dynamically. The
output of the programmable divider is fed to the phase
comparator where it is compared in both phase and frequency
domain with the comparison frequency. This frequency is
derived either from the on board crystal controlled oscillator or
from an external source. In both cases the reference
frequency is divided down to the comparison frequency by the
reference divider which is programmable into 1 of 8 ratios as
described in Table 1.
The output of the phase comparator feeds the charge
pump and loop amplifier section, which when used with an
external high voltage transistor and loop filter integrates the
current pulses into the varactor line voltage. The charge pump
current is selected by bit C0 as described in Table 3.
The phase comparator also drives the lock detect circuit
which generates a lock flag. 'In-lock' is indicated by a high
impedance state on the lock output.
The crystal frequency Fref is available at the REF output.
This may be used as the reference for a second synthesiser
as shown in Fig. 6. The REF output is disabled by connecting
the output, pin 3, to V
CC
.
4
SP5668
Phase Noise
The SP5668 has been designed to offer good phase noise
performance even when operated with a standard low profile
4MHz crystal and a high comparison frequency, e.g. 2MHz.
The typical phase noise performance measured in the
standard application is contained in Table 4. It has been
demonstrated that even higher levels of performance will be
achieved in a tuner application.
Test Modes
The programmable divider output divided by two Fpd/2 and
the comparison frequency Fcomp, can be switched to ports P0
and P1 respectively.
The charge pump can be forced to either source or sink
current, and may be disabled to high impedance state.
The varactor DRIVE output can be disabled by the OS bit
within the data word, so switching the external transistor 'OFF'
and allowing an external voltage to be written to the varactor
line for tuner alignment purposes.
The test modes are described in Table 2.
CLOCK
ENABLE
DATA
MSB
2
26
2
25
2
24
2
23
2
22
2
21
2
20
2
19
2
18
2
17
2
16
P2
P1
P0 TO OS CO R2
R1 R0 PE
FREQUENCY DATA
2
16
to 2
0
PE
R2
,
R1
,
R0
P2, P1, P0
CO
OS
T0
t : Programmable divider ratio control bits
:
÷2
Prescaler (Enable = 1, Disable = 0)
t : Reference divider ratio control bits (see Table 1)
t : Port control bits
t : Charge Pump current select (see Table 3)
t : Drive output disable switch
t : Test mode enable (see Table 2)
2
0
LSB
Figure 3 - Data format and timing
R2
0
0
0
0
1
1
1
1
R1
0
0
1
1
0
0
1
1
R0
0
1
0
1
0
1
0
1
RATIO
2
4
8
16
32
64
128
256
Comparison Frequency with a 4MHz
external reference
2MHz
1MHz
500kHz
250kHz
125kHz
62.5kHz
31.25kHz
15.625kHz
Table 1 - Reference division ratio
P1
X
0
0
1
1
X = Don't care
P0
X
0
1
0
1
T0
0
1
1
1
1
FUNCTIONAL DESCRIPTION
Normal operation
Charge pump sink. LOCK output = Lo Z
Charge pump source. LOCK output = Hi Z
Charge pump disable. LOCK output = Lo Z
Port P1 = Fcomp: Port 0 = Fpd/2
Table 2 - Test modes
5
