SP6336, SP6337,
& SP6338
Triple
µPower
Supervisory Circuit
with Watchdog and Power Fail
FEATURES
V1
1
2
8
RSTB
7
WDI
6
GND
5
■
■
■
■
■
■
■
■
■
■
Low operating voltage of 1.6V
Low operating current of 20µA typical
Monitors up to 3 supplies simultaneously
Adjustable inputs monitor down to 0.5V
Reset asserted down to 0.9V
2% accuracy over temperature range
Power Fail Input Functionality (PFI)
Power Fail Output function, active low (PFOB)
Open Drain (OD) or CMOS RSTB output
4 Reset Timeout Periods:
50ms, 100ms, 200ms and 400 ms
■
Watch Dog Input Functionality
■
Available in Lead Free, RoHS
Compliant Package: 8 pin TSOT
V2
SP6336
8 Pin TSOT
PFI
3
V3
4
PFOB
Open Drain RESET
SEE PAGE 2 FOR OTHER
AVAILABLE PINOUTS
DESCRIPTION
The
SP6336 - SP6337 - SP6338 Triple
µPower
Supervisory Circuit Family is a family of
microprocessor reset supervisory circuits with multiple reset voltages. The family provides
low voltage monitoring ability for up-to three supplies with two precision factory-set thresholds
and one user defined custom threshold. These circuits perform a single function: if any of
the input supply voltages drops below its associated threshold, reset outputs are asserted.
The products in the family offer power fail and watchdog functionalities. SP6336 , SP6337
& SP6338 are packaged in an 8-pin TSOT package. All devices are fully specified over -40
o
C
to +85
o
C temperature range.
TYPICAL APPLICATION CIRCUIT
Jun 4-06 Rev H
SP6336-SP6337-SP6338 Triple
µPower
Supervisory Circuit
© 2007 Sipex Corporation
1
V1
V2
1
2
SP6336
8 Pin TSOT
8
RSTB
7
WDI
6
GND
5
V1
V2
1
2
SP6337
8 Pin TSOT
8
RSTB
7
WDI
6
GND
5
PFOB
V1
V2
1
2
SP6338
8 Pin TSOT
8
RST
7
WDI
6
GND
5
PFOB
PFI
3
V3
4
PFI
3
V3
4
PFI
3
V3
4
PFOB
OPEN DRAIN RESET
CMOS RESET
CMOS RESET
PART
NUMBER
SP6336
SP6337
SP6338
V1
√
√
√
V2
√
√
√
√
√
√
V3
Reset
OD Active Low
CMOS Active Low
CMOS Active High
WatchDog
Input
√
√
√
Power
Fail
Input
√
√
√
Power Fail
Output
BAR
√
√
√
Feature and Pinout Diagram
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections
of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability
and cause permanent damage to the device.
Terminal Voltage (with respect to GND)
V1, V2.................................................... -0.3 to +6V
Open-Drain RSTB, PFOB........................-0.3 to +6V
CMOS RST, RSTB........................ -0.3 to (V1+0.3V)
Input Current/Output
Current..................................,,........................20mA
V3, V4, PFI, WDI...........................-0.3 to (V1+0.3V)
Operating Temperature
Range...............................................-40°C to +85°C
Storage Temperature
Range...............................................-65°C to 150°C
Thermal Resistance
θ
JA
.............................134°C/W
Jun 4-06 Rev H
SP6336-SP6337-SP6338 Triple
µPower
Supervisory Circuit
© 2007 Sipex Corporation
2
ELECTRICAL CHARACTERISTICS
PARAMETER
Operating Voltage Range
Supply Current
MIN
0.9
TYP
MAX
5.5
UNITS
V
uA
CONDITIONS
T
A
= -40ºC to +85ºC
V1 < 5.5V, V2 < 3.60V, all
I/O pins open
V1 < 3.6V, V2 < 2.75V, all
I/O pins open
Z (valid for V1 falling)
Y (valid for V1 falling)
X (valid for V1 falling)
W (valid for V1 falling)
V (valid for V1 falling)
U (valid for V1 falling)
T (valid for V1 falling)
S (valid for V1 falling)
R (valid for V1 falling)
J (valid for V2 falling)
I (valid for V2 falling)
H (valid for V2 falling)
G (valid for V2 falling)
F (valid for V2 falling)
E (valid for V2 falling)
D (valid for V2 falling)
C (valid for V2 falling)
B (valid for V2 falling)
A (valid for V2 falling)
V1 =1.6V to 5.5V; TA = -40ºC to +85ºC; unless otherwise noted. Typical values are at TA =+25ºC
20
15
4.532
4.287
3.013
2.866
2.572
2.273
2.146
1.636
1.548
2.266
2.144
1.631
1.543
1.360
1.286
1.087
1.029
0.816
0.772
4.625
4.375
3.075
2.925
2.625
2.320
2.190
1.670
1.580
2.313
2.188
1.665
1.575
1.388
1.313
1.110
1.050
0.833
0.788
0.06
0.04
0.65
0.5
50
50
50
100
200
400
500
1.5
30
25
4.718
4.463
3.137
2.984
2.678
2.367
2.234
1.704
1.612
2.360
2.232
1.698
1.607
1.416
1.340
1.133
1.071
0.850
0.804
V1 Reset Threshold
V
V2 Reset Threshold
V
Threshold 1 Tempco
Threshold 2 Tempco
Threshold 1 Hysteresis
Threshold 2 Hysteresis
V1 to RST/RSTB Delay
V2 to RST/RSTB Delay
Reset Timeout Period (T1)
37
Reset Timeout Period (T2)
74
Reset Timeout Period (T3)
148
Reset Timeout Period (T4)
296
V3 RESET COMPARATOR INPUT
V3 Input Threshold
490
V3 Input Current
-50
V3 Threshold Hysteresis
mV/ºC
mV/ºC
%
%
us
us
63
126
252
504
510
50
ms
ms
ms
ms
mV
nA
mV
reference to Vth1 typical
reference to Vth2 typical
V1 = Vth1 to (Vth1-0.1V),
Vth1 = 3.075
V2 = Vth2 to (Vth2-0.1V),
Vth2 = 1.575
TOPT-1
TOPT-2
TOPT-3
TOPT-4
T
A
= +25ºC
Jun 4-06 Rev H
SP6336-SP6337-SP6338 Triple
µPower
Supervisory Circuit
© 2007 Sipex Corporation
3
ELECTRICAL CHARACTERISTICS
(Continued)
PARAMETER
WDI – WATCHDOG INPUT
Watchdog Timeout Period
WDI Pulse Width
WDI Input Threshold
MIN
TYP
MAX
UNITS
CONDITIONS
V1 =1.6V to 5.5V; TA = -40ºC to +85ºC; unless otherwise noted. Typical values are at TA =+25ºC
1.2
0.1
2
0.4
sec
µs
V
WDI = 0.0V or V1
V1 = Vth1 - 0.1V, Isink =
1mA, output asserted
V_PFI=0.4, V1= , Isink =
1mA, PFOB output asserted
V
V
V1 = Vth1+0.1V, Isource =
1mA, output not asserted
V1 = Vth1-0.1V, Isource =
1mA, output asserted
V1 = Vth1+0.1V, V2 > Vth2,
V3 > 0.5 , V4 > 0.5 Isource
= 1mA, output not asserted
Output asserted
0.8*V1
µA
WDI Input Current
-500
+500
RESET & POWER FAIL OUTPUTS
RST / RSTB / WDOB / PFOB
RSTB
(CMOS or
0.4
V
OD)
PFOB
RSTB
RST
(CMOS)
(CMOS)
0.8*V1
0.8*V1
0.4
RST
(CMOS)
0.4
V
RSTB / WDOB / PFOB
Output Open-Drain Leakage
Current
PFI - POWER FAIL INPUT
PFI Input Threshold
PFI Input Current
PFI Hysteresis
PFI to PFOB Delay
2
nA
490
-50
500
2.5
4
510
50
mV
nA
mV
µs
Jun 4-06 Rev H
SP6336-SP6337-SP6338 Triple
µPower
Supervisory Circuit
© 2007 Sipex Corporation
4
PIN DESCRIPTION
Pin #
1
2
3
4
5
6
Name
V1
V2
PFI
V3
PFOB
GND
Description
First supply voltage input. Also powers internal circuitry. Trip
threshold
voltage
is
internally set.
Second supply voltage input. Trip threshold voltage internally set.
Power Fail Input pin. Trip threshold is 0.5V. When the input voltage at
the PFI pin is <0.5V, PFOB is low. Connect to GND or V1 if not used.
Input for the third supply voltage. Trip threshold is 0.5V.
Power Fail Output pin. Active low open drain output. When the input
voltage at the PFI pin is <0.5V, PFOB is low.
Common ground reference pin.
Watch-Dog Input pin. When no transition is detected at the WDI pin for
the duration of WDI timeout period, reset is asserted. Leave open if not
used. RST/RSTB output is used to signal watchdog timeout overflow,
and its output pulses high/low (depending on the active reset polarity)
for the reset timeout period after each watchdog timeout overflow. The
watchdog timer clears whenever the reset is asserted or manual reset
is asserted or a transition is observed at WDI pin. Watchdog timer
functionality can be disabled by leaving this input floating.
Reset output. Open-Drain or CMOS, active high or low. Reset is
asserted when any of the three supply inputs is below its trip threshold.
It stays asserted for 200 ms (typical / default) after the last supply input
traverses its trip threshold. Reset is guaranteed to be in the correct
state for V1>0.9V. RST/RSTB asserts when V1 or V2 or V3 drop below
their corresponding reset thresholds, or the watchdog timer triggers a
reset. RST/RSTB remains asserted for the reset timeout period after
V1 and V2 and V3 exceed their corresponding reset thresholds. Open-
drain outputs require an external pull-up resistor. CMOS outputs are
referenced to V1.
7
WDI
8
RST/RSTB
Jun 4-06 Rev H
SP6336-SP6337-SP6338 Triple
µPower
Supervisory Circuit
© 2007 Sipex Corporation
5
嵌入式系统
