SP6339, SP6341
Triple
µPower
Supervisory Circuit
with Manual Reset and Watchdog
FEATURES
■
■
■
■
■
■
■
■
■
■
■
■
V1
1
2
8
RSTB
7
MRIB
6
GND
5
Low operating
voltage of 1.6V
Low operating current of 20µA typical
Monitors up to 3 supplies simultaneously
Adjustable input monitors down to 0.5V
Reset asserted down to 0.9V
2% accuracy over temperature range
Open Drain (OD) or CMOS RSTB output
4 Reset Timeout Periods:
50mS, 100mS, 200mS, and 400mS
Watch Dog Timer Function -- WDI
Independent OD or CMOS Watchdog
Output (Active Low) -- WDOB
Manual Reset Input (Active Low) -- MRIB
8 Pin TSOT package
V2
SP6339
8 Pin TSOT
WDI
3
V3
4
WDOB
Open Drain RESET
SEE PAGE 2 FOR OTHER
AVAILABLE PINOUTS
Now Available in Lead Free Packaging
DESCRIPTION
SP6339-SP6341
Triple
µPower
Supervisory Circuit
Family is a family of microprocessor
reset supervisory circuits with multiple reset voltages. The family
provides low voltage
monitoring ability for up to three supplies with two precision factory-set thresholds and one
user defined custom threshold. These circuits perform a single function: if any of the input
supply
voltages drops below its associated threshold, reset outputs are asserted. Products
in the family offer manual reset and watchdog functionalities. SP6339 and SP6341 are
packaged in an 8-pin TSOT package. All devices are fully specified over -40
o
C to +85
o
C
temperature range.
TYPICAL APPLICATION CIRCUIT
Nov 20-06 Rev J
SP6339-SP6341 Triple
µPower
Supervisory Circuit
© Copyright 2006 Sipex Corporation
1
V1
V2
1
2
SP6339
8 Pin TSOT
8
RSTB
7
MRIB
6
GND
5
V1
V2
WDI
1
2
3
SP6341
8 Pin TSOT
8
RSTB
7
MRIB
6
GND
5
WDI
3
V3
4
WDOB
V3
4
WDOB
Open Drain RESET
CMOS RESET
PART
NUMBER
SP6339
SP6341
V1
√
√
V2
√
√
V3
√
√
Reset
OD Active Low
CMOS Active Low
MRIB
√
√
WDI
√
√
WDOB
OD Active Low
CMOS Active Low
Feature and Pinout Diagram
Representative Samples Available
Sipex
Product
SP6339
Product
Description
Package
V1
(Volts)
V2
(Volts)
V3
(Volts)
V4
(Volts)
Reset
(ms)
Ordering #
SP6339EK1-L-Z-J-C
Triple Supervisor
8 Pin TSOT
Open Drain low
4.625
2.313
0.5
N/A
200
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation
of the device at these ratings or any other above those
indicated in the operation sections of the specifica-
tions below is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods of time
may affect reliability and cause permanent damage to
the device.
Input Current/Output
Current.................................,,........................20mA
V3, MRIB, WDI........................-0.3 to (V1+0.3V)
Operating Temperature
Range...............................................-40°C to +85°C
Storage Temperature
Range...............................................-65°C to 150°C
Terminal Voltage (with respect to GND)
V1, V2.................................................... -0.3 to +6V
Open-Drain RSTB,
WDOB.....................................................-0.3 to +6V
Thermal Resistance
Θ
JA
..............................134°C/W
CMOS RST, RSTB,
WDOB........................................... -0.3 to (V1+0.3V)
Nov 20-06 Rev J
SP6339-SP6341 Triple
µPower
Supervisory Circuit
© Copyright 2006 Sipex Corporation
2
ELECTRICAL CHARACTERISTICS
PARAMETER
Operating Voltage
Range
Supply Current
MIN
0.9
TYP
MAX
5.5
UNITS
V
uA
CONDITIONS
T
A
= -40ºC to +85ºC
V1 < 5.5V, V2 < 3.60V, all I/O
pins open
V1 < 3.6V, V2 < 2.75V, all I/O
pins open
Z (valid for V1 falling)
Y (valid for V1 falling)
X (valid for V1 falling)
W (valid for V1 falling)
V (valid for V1 falling)
U (valid for V1 falling)
T (valid for V1 falling)
S (valid for V1 falling)
R (valid for V1 falling)
J (valid for V2 falling)
I (valid for V2 falling)
H (valid for V2 falling)
G (valid for V2 falling)
F (valid for V2 falling)
E (valid for V2 falling)
D (valid for V2 falling)
C (valid for V2 falling)
B (valid for V2 falling)
A (valid for V2 falling)
V1 = 1.6V to 5.5V; TA = -40ºC to +85ºC; unless otherwise noted. Typical values are at TA =+25ºC
20
15
4.532
4.287
3.013
2.866
2.572
2.273
2.146
1.636
1.548
2.266
2.144
1.631
1.543
1.360
1.286
1.087
1.029
0.816
0.772
4.625
4.375
3.075
2.925
2.625
2.320
2.190
1.670
1.580
2.313
2.188
1.665
1.575
1.388
1.313
1.110
1.050
0.833
0.788
0.06
0.04
0.65
0.5
50
50
37
74
148
296
50
100
200
400
30
25
4.718
4.463
3.137
2.984
2.678
2.367
2.234
1.704
1.612
2.360
2.232
1.698
1.607
1.416
1.340
1.133
1.071
0.850
0.804
V1 Reset
Threshold
V
V2 Reset
Threshold
V
Threshold 1
Tempco
Threshold 2
Tempco
Threshold 1
Hysteresis
Threshold 2
Hysteresis
V1 to RST/RSTB
Delay
V2 to RST/RSTB
Delay
Reset Timeout
Period (T1)
Reset Timeout
Period (T2)
Reset Timeout
Period (T3)
Reset Timeout
Period (T4)
mV/ºC
mV/ºC
%
%
us
us
63
126
252
504
ms
ms
ms
ms
reference to Vth1 typical
reference to Vth2 typical
V1 = Vth1 to (Vth1-0.1V), Vth1
= 3.075
V2 = Vth2 to (Vth2-0.1V), Vth2
= 1.575
TOPT-1
TOPT-2
TOPT-3
TOPT-4
Nov 20-06 Rev J
SP6339-SP6341 Triple
µPower
Supervisory Circuit
© Copyright 2006 Sipex Corporation
3
ELECTRICAL CHARACTERISTICS
PARAMETER
MIN
TYP
MAX
UNITS
CONDITIONS
V1 = 1.6V to 5.5V; T
A
= -40ºC to +85ºC; unless otherwise noted. Typical values are at T
A
=+25ºC
V3 RESET COMPARATOR INPUT
V3 Input Threshold
490
V3 Input Current
-50
V3 Threshold
Hysteresis
MRIB - MANUAL RESET INPUT
MRIB Input
Threshold
MRIB Input
0.8*V1
Threshold
MRIB Minimum
1
Input Pulse Width
MRIB Glitch
Rejection
MRIB to RST/RSTB
Delay
MRIB Pull-Up
30
Resistance
WDI - WATCHDOG INPUT
Watchdog Timeout
1.2
Period
WDI Pulse Width
0.1
WDI Input
Threshold
WDI Input
0.8*V1
Threshold
-500
WDI Input Current
RESET / WATCHDOG OUTPUTS
RSTB
(CMOS or OD)
RSTB (CMOS)
WDOB (CMOS or
OD)
0.8*V1
500
1.5
510
50
mV
nA
mV
T
A
= +25ºC
0.4
V
V
us
Vil
Vih
150
100
55
85
ns
ns
kΩ
1.6
2
sec
us
0.4
V
V
Vil
Vih
WDI = 0.0V or V1
V1 = Vth1 - 0.1V, Isink = 1mA,
output asserted
V1 = Vth1 + 0.1V, Isource =
1mA, output not asserted
WDI = 0.0V or V1, V1 > Vth1,
V2 > Vth2, V3 > 0.5, MRIB float,
Isink = 1mA, WDOB output
asserted
V1 > Vth1, V2 > Vth2, V3 > 0.5,
MRIB float, WDOB not
asserted, Isource = 1mA
T
A
= +25ºC
500
RSTB / WDOB
0.4
nA
V
V
0.4
V
WDOB (CMOS)
RSTB / WDOB
Output OD Leakage
Current
Nov 20-06 Rev J
0.8*V1
V
2
nA
SP6339-SP6341 Triple
µPower
Supervisory Circuit
© Copyright 2006 Sipex Corporation
4
PIN DESCRIPTION
Pin #
1
2
Name
V1
V2
Description
First supply voltage input. Also powers internal circuitry. Trip threshold
voltage internally set.
Second supply voltage input. Trip threshold voltage internally set.
Watch-Dog Input pin. When no transition is detected at the WDI pin for
the duration of WDI timeout period, reset is asserted. RSTB output is
used to signal watchdog timeout overflow -- RSTB output pulses
high/low (depending on the active reset polarity) for the reset timeout
period after each watchdog timeout overflow. WDOB remains at
“LOW” logic level after watchdog timeout period is expired and it
remains “LOW” until WDI makes a transition. RSTB output is not
affected by the watchdog functionality. The watchdog timer clears
whenever the reset is asserted or manual reset is asserted or a
transition is observed at WDI pin.
Input for the third supply voltage. Trip threshold is 0.5V.
Watch Dog Output. Open-Drain or CMOS, active LOW. If WDI
remains at “HIGH” or “LOW” logic level for longer than the
watchdog timeout period, the internal watchdog timer overflows and
WDOB is asserted. WDOB does not de-assert until the watchdog is
cleared via transition at the WDI pin. Another scenario for WDOB to
assert is when the reset output is asserted due to an under-voltage V1,
V2, V3 condition. WDO de-asserts without a reset timeout period.
Floating WDI will not disable watchdog timer in devices with dedicated
WDOB output. Open-drain WDOB outputs require an external pull-up
resistor. CMOS outputs are referenced to V1.
Common ground reference pin.
Manual Reset Input pin. Active low. It has an internal pull-up resistor.
Reset asserted when MRIB is pulled low and is kept asserted for
200ms after MRIB is released or pulled high. Leave open if not used.
Reset output. Open-Drain or CMOS, active low. Reset is asserted
when any of the three supply inputs is below its trip threshold. It stays
asserted for 200 ms (typical / default) after the last supply input
traverses its trip threshold. Reset is guaranteed to be in the correct
state for V1>0.9V. RSTB asserts when V1 or V2 or V3 drop below their
corresponding reset thresholds, or MRIB is pulled “LOW”. RSTB
remains asserted for the reset timeout period after V1 and V2 and V3
exceed their corresponding reset thresholds or MRIB goes “LOW”
to “HIGH”. Open-drain outputs require an external pull-up resistor.
CMOS outputs are referenced to V1.
3
WDI
4
V3
5
WDOB
6
7
GND
MRIB
8
RSTB
Nov 20-06 Rev J
SP6339-SP6341 Triple
µPower
Supervisory Circuit
© Copyright 2006 Sipex Corporation
5
