SP6340, SP6342
Dual
µPower
Supervisory
Circuit with Watchdog
FEATURES
■
■
■
■
■
■
■
Low operating voltage of 1.6V
Low operating current of 20µA typical
Monitors 2 supplies simultaneously
Reset asserted down to 0.9V
2% accuracy over temperature range
Open Drain (OD) or CMOS RSTB output
4 Reset Timeout Periods
50ms, 100ms 200ms, and 400ms
■
Watch Dog Timer Function
■
Independent Open Drain Watchdog Output
■
TSOT-6 package
Available in Lead Free Packaging
DESCRIPTION
SP6340 and SP6342
Dual
µPower
Supervisory
Circuit Family is a family of microprocessor
reset supervisory circuits with multiple reset voltages. The family provides low voltage
monitoring ability for up to two supplies with two precision factory-set thresholds. These
circuits perform a single function: if any of the input supply voltages drops below its
associated threshold, reset outputs are asserted. Products in the family offer watchdog
functionalities. SP6340 and SP6342 are packaged in a 6-pin TSOT package. All devices are
fully specified over -40
o
C to +85
o
C temperature range.
TYPICAL APPLICATION CIRCUIT
RSTB
GND
WDOB
6
5
4
SP6340
6 Pin TSOT
1
V1
2
V2
3
WDI
OPEN DRAIN RESET
SEE PAGE 2 FOR OTHER
AVAILABLE PINOUTS
Date: 4/10/06 Rev Dual
µPower
Supervisory Circuit Dual
µPower
Supervisory Circuit
SP6340 - SP6342
SP6340 - SP6342 J
© Copyright 2006 Sipex Corporation
© Copyright 2006 Sipex Corporation
1
RSTB
GND
WDOB
RSTB
GND
WDOB
6
5
4
6
5
4
SP6340
6 Pin TSOT
1
V1
SP6342
6 Pin TSOT
3
WDI
2
V2
1
V1
2
V2
3
WDI
OPEN DRAIN RESET
PART
NUMBER
SP6340
SP6342
V1
√
√
V2
√
√
Reset
OD Active Low
CMOS Active Low
CMOS RESET
WatchDog
Input
√
√
WatchDog Output
BAR
OD Active Low
CMOS Active Low
Feature and Pinout Diagram
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation
of the device at these ratings or any other above those
indicated in the operation sections of the specifica-
tions below is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods of time
may affect reliability and cause permanent damage to
the device.
Input Current/Output
Current.................................,,........................20mA
WDI...............................................-0.3 to (V1+0.3V)
Operating Temperature
Range...............................................-40°C to +85°C
Storage Temperature
Range...............................................-65°C to 150°C
Terminal Voltage (with respect to GND)
V1, V2.................................................... -0.3 to +6V
Open-Drain RSTB,
WDOB...............................................-0.3 to +6V
CMOS RSTB,
WDOB........................................... -0.3 to (V1+0.3V)
Thermal Resistance
Θ
JA
...............................134°C/W
Date: 4/10/06 Rev J
SP6340 - SP6342 Dual
µPower
Supervisory Circuit
© Copyright 2006 Sipex Corporation
2
ELECTRICAL CHARACTERISTICS
PARAMETER
Operating Voltage
Range
Supply Current
MIN
0.9
TYP
MAX
5.5
UNITS
V
uA
CONDITIONS
T
A
= -40ºC to +85ºC
V1 < 5.5V, V2 < 3.60V, all I/O
pins open
V1 < 3.6V, V2 < 2.75V, all I/O
pins open
Z (valid for V1 falling)
Y (valid for V1 falling)
X (valid for V1 falling)
W (valid for V1 falling)
V (valid for V1 falling)
U (valid for V1 falling)
T (valid for V1 falling)
S (valid for V1 falling)
R (valid for V1 falling)
J (valid for V2 falling)
I (valid for V2 falling)
H (valid for V2 falling)
G (valid for V2 falling)
F (valid for V2 falling)
E (valid for V2 falling)
D (valid for V2 falling)
C (valid for V2 falling)
B (valid for V2 falling)
A (valid for V2 falling)
V1 = 1.6V to 5.5V; TA = -40ºC to +85ºC; unless otherwise noted. Typical values are at TA =+25ºC
20
15
4.532
4.287
3.013
2.866
2.572
2.273
2.146
1.636
1.548
2.266
2.144
1.631
1.543
1.360
1.286
1.087
1.029
0.816
0.772
4.625
4.375
3.075
2.925
2.625
2.320
2.190
1.670
1.580
2.313
2.188
1.665
1.575
1.388
1.313
1.110
1.050
0.833
0.788
0.06
0.04
0.65
0.5
50
50
37
74
148
296
50
100
200
400
30
25
4.718
4.463
3.137
2.984
2.678
2.367
2.234
1.704
1.612
2.360
2.232
1.698
1.607
1.416
1.340
1.133
1.071
0.850
0.804
V1 Reset Threshold
V
V2 Reset Threshold
V
Threshold 1
Tempco
Threshold 2
Tempco
Threshold 1
Hysteresis
Threshold 2
Hysteresis
V1 to RST/RSTB
Delay
V2 to RST/RSTB
Delay
Reset Timeout
Period (T1)
Reset Timeout
Period (T2)
Reset Timeout
Period (T3)
Reset Timeout
Period (T4)
mV/ºC
mV/ºC
%
%
us
us
63
126
252
504
ms
ms
ms
ms
reference to Vth1 typical
reference to Vth2 typical
V1 = Vth1 to (Vth1-0.1V), Vth1
= 3.075
V2 = Vth2 to (Vth2-0.1V), Vth2
= 1.575
TOPT-1
TOPT-2
TOPT-3
TOPT-4
Date: 4/10/06 Rev J
SP6340 - SP6342 Dual
µPower
Supervisory Circuit
© Copyright 2006 Sipex Corporation
3
ELECTRICAL CHARACTERISTICS
(CONTINUED)
PARAMETER MIN
TYP
MAX
UNITS
CONDITIONS
V1 = 1.6V to 5.5V; T
A
= -40ºC to +85ºC; unless otherwise noted. Typical values are at T
A
=+25ºC
WDI - WATCHDOG INPUT
Watchdog Timeout
1.2
1.6
Period
WDI Pulse Width
0.1
WDI Input
Threshold
WDI Input
0.8*V1
Threshold
WDI Input Current
-500
RESET / WATCHDOG OUTPUTS
RSTB
(CMOS or OD)
RSTB (CMOS)
WDOB (CMOS or
OD)
WDOB (CMOS)
RSTB / WDOB
Output OD Leakage
Current
0.8*V1
2
0.8*V1
2
sec
us
0.2*V1
V
V
Vil
Vih
WDI = 0.0V or V1
V1 = Vth1 - 0.1V, Isink = 1mA,
output asserted
V1 = Vth1 + 0.1V, Isource =
1mA, output not asserted
WDI = 0.0V or V1, V1 > Vth1,
V2 > Vth2, Isink = 1mA,
WDOB output asserted
V1 > Vth1, V2 > Vth2, WDOB
not asserted, Isource = 1mA
T
A
= +25ºC
500
nA
RSTB / WDOB
0.4
V
V
0.4
V
V
nA
Date: 4/10/06 Rev J
SP6340 - SP6342 Dual
µPower
Supervisory Circuit
© Copyright 2006 Sipex Corporation
4
PIN DESCRIPTION
Pin #
1
2
Name
V1
V2
Description
First supply voltage input. Also powers internal circuitry. Trip
threshold voltage internally set.
Second supply voltage input. Trip threshold voltage internally set.
Watch-Dog Input pin. When no transition is detected at the WDI pin
for the duration of WDI timeout period, reset is asserted. WDOB
remains at “LOW” logic level after watchdog timeout period is
expired and it remains “LOW” until WDI makes a transition.
RST/RSTB output is not affected by the watchdog functionality in the
parts with separate WDOB output. The watchdog timer clears
whenever the reset is asserted or a transition is observed at WDI pin.
Watch Dog Output. Open-Drain or CMOS, active LOW. If WDI
remains at “HIGH” or “LOW” logic level for longer than the
watchdog timeout period, the internal watchdog timer overflows and
WDOB is asserted. WDOB does not de-assert until the watchdog is
cleared via transition at the WDI pin. Another scenario for WDOB to
assert is when the reset output is asserted due to an under-voltage
V1 or V2 condition. WDO de-asserts without a reset timeout period.
Floating WDI will not disable watchdog timer in devices with
dedicated WDOB output. Open-drain WDOB outputs require an
external pull-up resistor. CMOS outputs are referenced to V1.
Common ground reference pin.
Reset output. Open-Drain or CMOS, active high or low. Reset is
asserted when any of the supply inputs is below its trip threshold. It
stays asserted for 200 ms (typical / default) after the last supply input
traverses its trip threshold. Reset is guaranteed to be in the correct
state for V1>0.9V. RSTB asserts when V1 or V2 drop below their
corresponding reset thresholds. RSTB remains asserted for the
reset timeout period after V1 and V2 exceed their corresponding
reset thresholds. Open-drain outputs require an external pull-up
resistor. CMOS outputs are referenced to V1.
3
WDI
4
WDOB
5
GND
6
RSTB
Date: 4/10/06 Rev J
SP6340 - SP6342 Dual
µPower
Supervisory Circuit
© Copyright 2006 Sipex Corporation
5
电子竞赛
