ADVANCE INFORMATION
DS3644-1·2
SP8680A
550MHz410/11
4
The SP8680A is an ECL variable modulus divider, with ECL
and TTL compatible outputs. The circuit can operate from
either ECL or TTL supplies. It divides by 10 when either of the
ECL control inputs, PE1 or PE2, is in the high state and by 11
when both are low (or open circuit). The divider can be set
asynchronously to the eleventh state by applying a high level
to the master set (MS) input.
CLOCK INHIBIT
CONTROL INPUTS
1
2
3
4
16
15
14
13
CLOCK INPUT
INPUT BIAS
MASTER SET INPUT
V
EE
(TTL O/P)
V
EE
TTL OUTPUT
NC
ECL OUTPUT
PE1
PE2
V
CC
FEATURES
s
Very High Speed – 650MHz (Typ.)
SP8680A
5
6
7
8
12
11
10
O/P STAGE V
CC
A
PE1 PULLUP
PE2 PULLUP
ECL OUTPUT
s
ECL and TTL Compatible Inputs/Outputs
s
DC or AC Clocking
s
Clock Inhibit
s
Asynchronous Master Set
s
Equivalent to Fairchild 11C90
QUICK REFERENCE DATA
s
Supply Voltage:
24·75V
to
25·5V
(ECL),
4·75V to 5·5V (TTL)
9
DG16
Fig. 1 Pin connections - top view
s
Power Consumption: 420mW
s
Temperature Range:
255°C
to
1125°C
ABSOLUTE MAXIMUM RATINGS
Supply voltage, |V
CC
2V
EE
|
ECL output source current
Storage temperature range
Max. junction temperature
TTL output sink current
Max. clock input voltage
8V
50mA
265°C
to
1150°C
1175°C
30mA
2·5V p-p
ORDERING INFORMATION
SP8680 A DG
V
CC
4
V
CC
A
5
11
TTL
OUTPUT
PE1 PULLUP
6
D1
Q1
D2
CK
S
7
1
16
S
Q2
D3
CK
S
Q3
D4
CK
S Q4
9
OUTPUT
Q4
8
OUTPUT
PE1
PE2
2
3
CK
PE2 PULLUP
CLOCK INHIBIT
CLOCK INPUT
BIAS GEN
14
MASTER SET
15
INPUT BIAS
12
V
EE
13
TTL V
EE
Fig. 2 Functional diagram
SP8680A
ELECTRICAL CHARACTERISTICS
Unless otherwise stated, the Electrical Characteristics are guaranteed over specified supply, frequency and temperature range
ECL OPERATION
Supply voltage, V
EE
=
24·75V
to
2
5·5V, V
CC
= 0V
Temperature, T
AMB
=
255°C
to
1125°C
Characteristic
Value
Symbol
f
MAX
f
MIN
I
EE
V
OH
V
OL
V
INH
V
INL
I
IL
I
H
I
H
t
pHL
t
pLH
t
pLH
t
s
t
r
t
ELH
t
EHL
Min.
550
Max.
MHz
MHz
10
mA
105
V
20·78
V
21·62
V
20·81
V
21·475
µA
µA
400
µA
250
ns
4
ns
3
ns
6
ns
ns
ns
2
ns
2
AC coupled clock = 350mV p-p
AC coupled clock = 600mV p-p
V
EE
=
25·5V,
pins 6, 7, 13 o/c
V
EE
=
25·2V
(25°C), R
L
= 100Ω to
22V
V
EE
=
25·2V
(25°C), R
L
= 100Ω to
22V
V
EE
=
25·2V
(25°C)
V
EE
=
25·2V
(25°C)
25°C
V
IN
=
21·85V
(25°C)
V
IN
=
20·8V
(25°C)
R
L
= 100Ω to
22V
(25°C)
R
L
= 100Ω to
22V
(25°C)
25°C
25°C
25°C
25°C
25°C
5
6
5
Units
Conditions
Notes
Maximum frequency (sinewave input)
Minimum frequency (sinewave input)
Power supply current
ECL output high voltage
ECL output low voltage
Input high voltage
Input low voltage
Input low currents
Input high current, clock and MS
Input high current, PE1 and PE2
Propagation delay, clock to Q4 low
Propagation delay, clock to Q4 high
Propagation delay, MS to Q4 high
Modulus control set-up time
Modulus control release time
ECL output rise time (20% - 80%)
ECL output fall time (80% - 20%)
20·93
21·85
20·095
21·85
0·5
4
4
6
6
6
3, 6
4, 6
6
6
TTL OPERATION
Supply voltage, V
CC
= V
CC
A = 4·75V to 5·5V, V
EE
= 0V
Temperature, T
AMB
=
255°C
to
1125°C
Characteristic
Value
Symbol
f
MAX
f
MIN
I
CC
V
OH
V
OL
V
INH
V
INL
I
IL
t
pHL
t
pLH
t
p
t
s
t
r
t
TLH
t
THL
Min.
550
10
111
2·3
0·5
3·9
3·5
24
6
6
4
4
5
5
14
14
17
Max.
MHz
MHz
mA
V
V
V
V
mA
ns
ns
ns
ns
ns
ns
ns
AC coupled clock = 350mV p-p
AC coupled clock = 600mV p-p
V
CC
= 5·5V, pins 6, 7 o/c, pin 13 to pin 12
V
CC
= 4·75V, I
OH
=
2640µA
V
CC
= 5·5V, I
OL
=
220µA
V
CC
= 5·0V (25°C)
V
CC
= 5·0V (25°C)
V
CC
= 5·5V (25°C), pins 6, 7 = V
CC
,
V
IN
= 0·4V
V
CC
= 5·0V (25°C)
V
CC
= 5·0V (25°C)
V
CC
= 5·0V (25°C)
V
CC
= 5·0V (25°C)
V
CC
= 5·0V (25°C)
V
CC
= 5·0V (25°C)
V
CC
= 5·0V (25°C)
5
6
5
5
5
Units
Conditions
Notes
Maximum frequency (sinewave input)
Minimum frequency (sinewave input)
Power supply current
TTL output high voltage
TTL output low voltage
Input high voltage, PE1 and PE2
Input low voltage, PE1 and PE2
Input low current, PE1 and PE2
Propagation delay, clock to TTL low
Propagation delay, clock to TTL high
Propagation delay, MS to TTL high
Modulus control set-up time
Modulus control release time
TTL output rise time (20% - 80%)
TTL output fall time (80% - 20%)
6
6
6
3, 6
4, 6
6
6
NOTES
1. The temperature coefficients of V
OH
=
11·2mV/°C,
V
OL
=
10·24mV/°C
and of V
IN
=
10·8mV/°C.
2. The test configuration for dynamic testing is shown in Fig.6.
3. The set-up time t
s
is defined as the minimum time that can elapse between L→H transition of control input and the next L→H clock pulse transition
to ensure that the
410
mode is obtained.
4. The release time t
r
is defined as the minimum time that can elapse between H→L transition of control input and the next L→H clock pulse transition
to ensure that the
411
mode is obtained.
5. Tested at
125°C
and
1125°C
only.
6. Guaranteed but not tested.
2
SP8680A
1600
INPUT AMPLITUDE (mV p-p)
1400
1200
1000
800
600
400
200
0
0
100
200
300
400
500
INPUT FREQUENCY (MHz)
600
700
800
255°C
1125°C
Fig. 3 Typical input sensitivity
Clock
inhibit
X
H
L
L
L
L
Output
response
All outputs
set high
Hold
411
410
410
410
CLOCK INPUT
MS
t
r
t
s
PE1
X
X
L
H
L
H
PE2
X
X
L
L
H
H
H
L
L
L
L
L
PE INPUT
6
Q4 AND TTL
5
5
Fig. 4 Truth table and timing diagram
j1
j
0.5
j2
j
0.2
j5
0
0.2
0.5
1
2
5
100
200
2
j
5
2
j
0.2
600
400
500
300
2
j
0.5
2
j
1
2
j
2
Fig. 5 Typical input impedance. Test conditions: Supply Voltage = 5V,
Ambient Temperature = 25°C. Frequencies in MHz, impedances normalised to 50Ω.
3
SP8680A
V
CC
160
160
160
200
TTL OUTPUT
15
INPUT FROM
GENERATOR
33
TO
MONITOR
33
12
20
V
EE
V
EE
(TTL)
13
16
4
5
11
Q4
8
9
200
ECL OUTPUT TO 50
Ω
200
ECL OUTPUT TO
TO SAMPLING SCOPE
DUT
Q4
Fig. 6 Test circuit
OPERATING NOTES
1. The clock input, which is ECL10K compatible throughout
the temperature range
255°C
to
1125°C,
can also be
coupled to TTL as shown in Fig. 9. The clock can also be
capacitively coupled to the signal source (see Fig, 7).
Connecting the internally-generated bias voltage to the
clock input i.e., pin 15 to pin 16, centres the clock input about
the switching threshold (see Fig. 8).
2. The two complementary outputs are ECL10K compatible
but internal pulldown resistors are not included and therefore
external pulldown resistors to V
EE
are required.
0·1µ
16
SP8680
15
3. The TTL totem pole output operates with the same supply
and is powered up by connecting V
EE
(pin 12) to TTL V
EE
(pin
13). If the TTL output is not required then the TTL V
EE
pin
should be left open circuit, reducing the power consumption
by 20mW, typically.
4. Both control inputs (PE1 and PE2) are ECL10K compatible
throughout the temperature range. Each control input is provided
with a pullup resistor, the remote ends of which are connected
to pins 6 and 7, respectively. This allows the pullup resistors
to be unused if so desired or to be used to interface from TTL
(see Fig. 9). If interfacing to ECL is required then pins 6 and 7
should be left open circuit; alternatively, they can be connected
to V
EE
to act as pulldown resistors. When high, the master set
input sets the divider to the eleventh state, is asynchronous
and overrides the clock input.
5. All the inputs have internal 50kΩ pulldown resistors.
6. The circuit will operate down to DC but inputslew rate
must be better than 20V/µs.
7. Input impedance is a function of frequency. See Fig. 5.
Fig. 7. AC coupled input
TTLMODULUS
CONTROL
V
CC
2 (3)
2k
6 (7)
V
CC
A
5
15V
0·1µ
0·1µ
CLOCK
INPUT
16
DIVIDE BY
10/11
50k
400
BIAS
GEN
13
10
TTL OUTPUT
50k
15
12
V
EE
V
EE
(TTL)
Fig. 8 Typical application showing TTL interfacing.
4
SP8680A
V
CC
270
V
CC
6 OR 7
2k
TTL
2 OR 3
(a) LOW SPEED
V
EE
6 OR 7
(a) HIGH SPEED
470
TTL
2 OR 3
2k
Fig. 9 TTL interface to PE1 and PE2
5
