SP9380
Complete Buffered 18-Bit D AC
Sipex D ata Converter Line
FEA TURES
• Complete 18-Bit DA C Including an Internal
Reference and an Output A mplifier
• Input Latches A ssist in M icroprocessor Interface
• Low Nonlinearity:
±1/2 LSB 18-Bit Differential
±1/2 LSB 18-Bit Integral
• 18-Bit M onotonicity
• Low Power: 600 mW Typ
• High Stability Over Time and Temperature
DESCRIPTION
The Sipex SP9380 is a complete voltage output DA C
offering 18-bit resolution (1 part in 262,144) and true
18-bit accuracy in a component size hybrid package.
The SP9380 comes complete with input latches, an
internal reference and a very low noise output
amplifier. The analog output ranges are pin
programmable for 0 to +5V . 0 to + 10V . ±5V and
±10V .
Using decoding techniques and ultrastable resistor
technology, the SP9380 exhibits typical nonlinearities
of ±0.5LSB (differential and integral) and high
stability over time and temperature. The power
dissipation is 600mW typical.
The device is available for either commerical (0ºC to
+70ºC) or military (–55ºC to +125ºC) applications in a
32-pin triple DIP.
FUNCTIONA L DIA GRA M
HEN
DB17
(M SB)
DB2
DB17
DB1 (M SB)
9
8
BIPOLA R
OFFSET
27
10V
SPA N
28
20V
SPA N
29
25 • • • • • • • • 10
INPUT
REGISTER
INPUT
REGISTER
20k
10k
LEN
6
10k
REF IN
26
18-BIT M DA C
–
10k
–
+
+
31
OUTPUT
REF OUT
1
REFERENCE
SP9380
10
GA IN
A DJUST
5
DIG
GND
32
A NA
GND
32
– 15V
32
+15V
32
SUM M ING
JUNCTION
165 Cedar Hill Street, Marlborough, MA 01752 Tel: 508.485.6350
www.satconelectronics.com
Fax: 508.485.5168
SPECIFICATIO N S
(Typical @25ºC and rated supplies.)
M ODEL
RESOLUTION
DIGITA L INPUTS
Unipolar Coding
Bipolar Coding
Logic
Compatibility
1
Input Leakage Current
2
Data Setup
3
Latch W idth
Data Hold
4
A CCURA CY
Differential Nonlinearity
Integral Nonlinearity
5
M onotonicity
INITIA L ERRORS
Gain
Offset
Unipolar
Bipolar
STA BILITY (ppm/º C)
Differential Nonlinearity
Integral Nonlinearity
Gain
Offset
Unipolar
Bipolar
STA BILITY LONG TERM
Differential Linearity
Gain
Offset
W A RM -UP TIM E
DY NA M IC PERFORM A NCE
A nalog Settling Time (1/2 LSB)
10 V olt Step
20 V olt Step
LSB Change
Slew Rate
M ajor Carry Transition Settling
to 0.006% FSR Strobed
REFERENCE
V oltage
Drift
Stability
A NA LOG OUTPUT
V oltage
Noise (W ideband)
+5V , +10V , ±5V , ±10V
0.0004% FSR p-p
+10V (internal)
5ppm/ºC
1 mV /year
30µsec
50µsec
8µsec
2V /µsec
10µS
16ppm/168hrs. @125ºC
1ppm/I000hrs. @25ºC
15ppm/I000hrs. @25ºC
15ppm/I000hrs. @25ºC
10 minutes
±0.1 typ. 0.4 max
±0.2 typ. ±0.4 max
±3 typ. ±7 max
±0.1 typ. ±0.5 max
±1 typ. ±4 max
±0.01% typ. ±0.10% max
±0.01% typ. ±0.05% max
±0.01% typ. ±0.05% max
±0.0002%
±0.0004%
±0.0002%
±0.0004%
18-Bits
FSR
FSR
FSR
FSR
typ.
max.
typ,
max,
±0.0008%
±0.0016%
±0.0010%
±0.0016%
16-Bits
FSR
FSR
FSR
FSR
typ.
max.
typ.
max.
Binary
Offset Binary
TTL CM OS
±1.0µA
150 nsec
170 nsec
100 nsec
18-Bits
SP9380-18
SP9380-16
SPECIFICA TION (Continued)
POW ER SUPPLY REQUIREM ENTS
+ 15V DC (±5% )
–15V DC (±5% )
Power Dissipation
Supply Rejection
TEM PERA TURE RA NGE
Operating
Storage
PA CK A GE
–55 to +125ºC
–65 to +150ºC
32 Pin M etal
30mA max
20mA max
600mW
±0.0001% /%
NOTES: 1. Digital input must not exceed supply voltage or go below 0.5V . 2. V IL 0.4, V HL 3.2.
3. Time that data must be stable before latch control goes to 0. 4. Time that data must be stable after latch control goes to 0.
5. Intearal Linearity, for this product, is measured as the arithmetic mean value of the magnitudes of the greatest positive deviation and the
greatest negative deviation from the theoretical value for any given input combination.
PA CK A GE OUTLINE
1.145 (29.08)
1.155.(29.34)
DIM ENSIONS
inches
(mm)
0.120 (3.05)
0.130.(3.30)
0.20 (5.08)
0.25.(6.35)
1.735 (44.07)
1.745.(44.23)
PIN DESIGNA TIONS
PIN
1
2
0.190 (4.85)
0.200.(5.08)
FUNCTION
REF OUT
GA IN A DJUST
+15V
-15V
DIG GND
LEN
HEN
DBO (LSB)
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
PIN
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
FUNCTION
A NA GND
OUTPUT
SUM M ING JUNCTION
20V SPA N
10V SPA N
BIPOLA R OFFSET
REF IN
DB17 (M SB)
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
INDICA TES PIN 1
1
0.900
(22.86)
32
3
4
5
6
7
8
9
10
0.095 (2.41)
0.105.(2.67)
16
17
0.125
(3.2)
TOP V IEW
11
12
13
14
15
16
OPERA TING INSTRUCTIONS
POW ER SUPPLY A ND
GROUNDING CONSIDERA TIONS
Clearly, the management of IR drops, power supply
noise, thermal stability and environmental noise
become critical issues when designing an 18-bit system.
To optimize the absolute accuracy of a high resolution
system, the following rules of thumb have to be followed:
1. Selection of low noise operation power supplies.
2. Proper decoupling of the supplies at the DA C using
10µF ceramic disk capacitor.
3. Usage of the “ holy point” grounding technique.
4. “ K elvin-sensed-output” connection of the DA C
the load.
Consult factory for application information.
ORDERING INFORM A TION
M ODEL
SP9380C-18
SP9380C-16
SP9380B-18
SP9380B-16
TEM PERA TURE
RA NGE
0 Cto70
0 Cto70
–55 C to +125 C
–55 C to +125 C
SCREENING
–
–
M IL-STD-883C
M IL-STD-883C
