Technical Data
Advance Information
DSP56L307/D
Rev. 3, 4/2003
24-Bit Digital Signal
Processor
3
16
6
6
Memory Expansion Area
Program
RAM
16 K
×
24 bits
or
15 K
×
24 bits
and
Instruction
Cache
1024
×
24 bits
PM_EB
SCI
Triple
Timer
HI08
ESSI
EFCOP
X Data
RAM
24 K
×
24 bits
Y Data
RAM
24 K
×
24 bits
The DSP56L307 is
intended for
applications requiring
a large amount of
on-chip memory, such
as networking and
wireless infrastructure
applications. The
EFCOP can accelerate
general filtering
applications, such as
echo-cancellation
applications,
correlation, and
general-purpose
convolution-based
algorithms.
PIO_EB
XM_EB
Address
Generation
Unit
Six Channel
DMA Unit
Bootstrap
ROM
YAB
XAB
PAB
DAB
YM_EB
Peripheral
Expansion Area
External
Address
Bus
Switch
External
Bus
Interface
and
I - Cache
Control
External
Data
Bus
Switch
Power
Management
JTAG
OnCE™
18
Address
24-Bit
DSP56300
Core
DDB
YDB
XDB
PDB
GDB
13
Control
Internal
Data
Bus
Switch
24
Data
Clock
PLL
Generator
EXTAL
XTAL
RESET
PINIT/NMI
Program
Interrupt
Controller
Program
Decode
Controller
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
Program
Address
Generator
Data ALU
24
×
24 + 56
→
56-bit MAC
Two 56-bit Accumulators
56-bit Barrel Shifter
5
DE
PCAP
Figure 1.
DSP56L307 Block Diagram
The Motorola DSP56L307, a member of the
DSP56300 Digital Signal Processor (DSP) family,
supports network applications with general
filtering operations. The Enhanced Filter
Coprocessor (EFCOP) executes filter algorithms in
parallel with core operations, enhancing signal
quality with no impact on channel throughput or
total channels supported. The result is increased
overall performance. Like the other DSP56300
family members, the DSP56L307 uses a
high-performance, single-clock-cycle-per-
instruction engine (DSP56000 code-compatible), a
barrel shifter, 24-bit addressing, an instruction
cache, and a direct memory access (DMA)
controller (see
Figure 1).
The DSP56L307
performs at 160 million instructions per second
(MIPS), attaining 290 MIPS when the EFCOP is in
use. It operates with an internal 160 MHz clock
with a 1.8 volt core and independent 3.3 volt
input/output (I/O) power.
Note:
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Table of Contents
DSP56L307 Features ......................................................................................................................................... iii
Target Applications ..............................................................................................................................................v
Product Documentation........................................................................................................................................v
Chapter 1
Signal/ Connection Descriptions
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.10
1.11
1.12
1.13
Signal Groupings.............................................................................................................................................. 1-1
Power................................................................................................................................................................ 1-3
Ground.............................................................................................................................................................. 1-3
Clock ................................................................................................................................................................ 1-4
PLL................................................................................................................................................................... 1-4
External Memory Expansion Port (Port A)...................................................................................................... 1-5
Interrupt and Mode Control ............................................................................................................................. 1-8
Host Interface (HI08) ....................................................................................................................................... 1-9
Enhanced Synchronous Serial Interface 0 (ESSI0)........................................................................................ 1-13
Enhanced Synchronous Serial Interface 1 (ESSI1)........................................................................................ 1-14
Serial Communication Interface (SCI)........................................................................................................... 1-16
Timers............................................................................................................................................................. 1-17
JTAG and OnCE Interface ............................................................................................................................. 1-18
Introduction ...................................................................................................................................................... 2-1
Maximum Ratings............................................................................................................................................ 2-1
Thermal Characteristics ................................................................................................................................... 2-2
DC Electrical Characteristics ........................................................................................................................... 2-3
AC Electrical Characteristics ........................................................................................................................... 2-4
Pin-Out and Package Information .................................................................................................................... 3-1
MAP-BGA Package Description ..................................................................................................................... 3-2
MAP-BGA Package Mechanical Drawing .................................................................................................... 3-10
Thermal Design Considerations....................................................................................................................... 4-1
Electrical Design Considerations ..................................................................................................................... 4-2
Power Consumption Considerations ................................................................................................................ 4-4
PLL Performance Issues .................................................................................................................................. 4-5
Input (EXTAL) Jitter Requirements................................................................................................................. 4-5
Chapter 2
Specifications
2.1
2.2
2.3
2.4
2.5
Chapter 3
Packaging
3.1
3.2
3.3
Chapter 4
Design Considerations
4.1
4.2
4.3
4.4
4.5
Appendix A
Index
Power Consumption Benchmark
Data Sheet Conventions
OVERBAR
“asserted”
“deasserted”
Examples:
Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when
low.)
Means that a high true (active high) signal is high or that a low true (active low) signal is low
Means that a high true (active high) signal is low or that a low true (active low) signal is high
Signal/Symbol
PIN
PIN
PIN
PIN
Logic State
True
False
True
False
Signal State
Asserted
Deasserted
Asserted
Deasserted
Voltage
V
IL
/V
OL
V
IH
/V
OH
V
IH
/V
OH
V
IL
/V
OL
Note:
Values for V
IL
, V
OL
, V
IH
, and V
OH
are defined by individual product specifications.
ii
DSP56L307 Features
High-Performance DSP56300 Core
• 160 million instructions per second (MIPS) (290 MIPS using the EFCOP in filtering applications) with
a 160 MHz clock at 1.8 V core and 3.3 V I/O
• Object code compatible with the DSP56000 core with highly parallel instruction set
• Data Arithmetic Logic Unit (Data ALU) with fully pipelined 24
×
24-bit parallel
Multiplier-Accumulator (MAC), 56-bit parallel barrel shifter (fast shift and normalization; bit stream
generation and parsing), conditional ALU instructions, and 24-bit or 16-bit arithmetic support under
software control
• Program Control Unit (PCU) with Position Independent Code (PIC) support, addressing modes
optimized for DSP applications (including immediate offsets), on-chip instruction cache controller,
on-chip memory-expandable hardware stack, nested hardware DO loops, and fast auto-return interrupts
• Direct Memory Access (DMA) with six DMA channels supporting internal and external accesses;
one-, two-, and three-dimensional transfers (including circular buffering); end-of-block-transfer
interrupts; and triggering from interrupt lines and all peripherals
• Phase Lock Loop (PLL) allows change of low-power Divide Factor (DF) without loss of lock and
output clock with skew elimination
• Hardware debugging support including On-Chip Emulation (OnCE) module, Joint Test Action
Group (JTAG) Test Access Port (TAP)
Enhanced Filtering Coprocessor (EFCOP)
• On-chip 24
×
24-bit filtering and echo-cancellation coprocessor that runs in parallel to the DSP core
• Operation at the same frequency as the core (up to 160 MHz)
• Support for a variety of filter modes, some of which are optimized for cellular base station applications:
— Real Finite Impulse Response (FIR) with real taps
— Complex FIR with complex taps
— Complex FIR generating pure real or pure imaginary outputs alternately
— A 4-bit decimation factor in FIR filters, thus providing a decimation ratio up to 16
— Direct form 1 (DFI) Infinite Impulse Response (IIR) filter
— Direct form 2 (DFII) IIR filter
— Four scaling factors (1, 4, 8, 16) for IIR output
— Adaptive FIR filter with true least mean square (LMS) coefficient updates
— Adaptive FIR filter with delayed LMS coefficient updates
On-Chip Peripherals
• Enhanced DSP56000-like 8-bit parallel host interface (HI08) supports a variety of buses (for example,
ISA) and provides glueless connection to a number of industry-standard microcomputers,
microprocessors, and DSPs
• Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three transmitters
(allows six-channel home theater)
• Serial communications interface (SCI) with baud rate generator
• Triple timer module
• Up to 34 programmable general-purpose input/output (GPIO) pins, depending on which peripherals are
enabled
iii
On-Chip Memories
• 192
×
24-bit bootstrap ROM
• 64 K RAM total
• Program RAM, Instruction Cache, X data RAM, and Y data RAM sizes are programmable:
Program
RAM Size
16 K
×
24-bit
15 K
×
24-bit
48 K
×
24-bit
47 K
×
24-bit
40 K
×
24-bit
39 K
×
24-bit
32 K
×
24-bit
31 K
×
24-bit
24 K
×
24-bit
23 K
×
24-bit
Instruction
Cache Size
0
1024
×
24-bit
0
1024
×
24-bit
0
1024
×
24-bit
0
1024
×
24-bit
0
1024
×
24-bit
X Data RAM Size* Y Data RAM Size*
24 K
×
24-bit
24 K
×
24-bit
8 K
×
24-bit
8 K
×
24-bit
12 K
×
24-bit
12 K
×
24-bit
16 K
×
24-bit
16 K
×
24-bit
20 K
×
24-bit
20 K
×
24-bit
24 K
×
24-bit
24 K
×
24-bit
8 K
×
24-bit
8 K
×
24-bit
12 K
×
24-bit
12 K
×
24-bit
16 K
×
24-bit
16 K
×
24-bit
20 K
×
24-bit
20 K
×
24-bit
Instruction
Cache
disabled
enabled
disabled
enabled
disabled
enabled
disabled
enabled
disabled
enabled
Switch
Mode
disabled
disabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
MSW1
0/1
0/1
0
0
0
0
1
1
1
1
MSW0
0/1
0/1
0
0
1
1
0
0
1
1
*Includes 4 K
×
24-bit shared memory (that is, memory shared by the core and the EFCOP)
Off-Chip Memory Expansion
• Data memory expansion to two 256 K
×
24-bit word memory spaces using the standard external
address lines
• Program memory expansion to one 256 K
×
24-bit words memory space using the standard external
address lines
• External memory expansion port
• Chip Select Logic for glueless interface to static random access memory (SRAMs)
• On-chip DRAM Controller for glueless interface to dynamic random access memory (DRAMs) up to
100 MHz operating frequency
Reduced Power Dissipation
•
•
•
•
Very low-power CMOS design
Wait and Stop low-power standby modes
Fully static design specified to operate down to 0 Hz (dc)
Optimized power management circuitry (instruction-dependent, peripheral-dependent, and
mode-dependent)
Packaging
The DSP56L307 is available in a 196-pin MAP-BGA package.
iv
Target Applications
•
•
•
•
•
Wireless and wireline infrastructure applications
Multi-channel wireless local loop systems
DSP resource boards
High-speed modem banks
Packet telephony
Product Documentation
The three documents listed in the following table are required for a complete description of the
DSP56L307 and are necessary to design properly with the part. Documentation is available from the
following sources. (See the back cover for details.)
•
•
•
•
A local Motorola distributor
A Motorola semiconductor sales office
A Motorola Literature Distribution Center
The World Wide Web (WWW)
Table 1.
DSP56L307 Documentation
Name
DSP56300 Family
Manual
DSP56L307 User’s
Manual
DSP56L307
Technical Data
Description
Detailed description of the DSP56300 family processor core and
instruction set
Detailed functional description of the DSP56L307 memory
configuration, operation, and register programming
DSP56L307 features list and physical, electrical, timing, and
package specifications
Order Number
DSP56300FM/AD
DSP56L307UM/D
DSP56L307/D
v
stm32/stm8
