Freescale Semiconductor
Data Sheet: Advance Information
Document Number: MPC5606S
Rev. 1, 10/2008
MPC5606S
LQFP–144
MAPBGA–225
QFN12
20
15 mm x 15 mm mm x 20 mm ##_mm_x_##mm
MPC560xS Microcontroller
Data Sheet
SOT-343R
##_mm_x_##mm
LQFP–176
24 mm x 24 mm
TBD
PKG-TBD
## mm x ## mm
32-bit MCU for cluster applications with stepper motor, TFT
graphic controller and LCD driver
The MPC5606S family of devices is designed to enable the development of automotive instrument cluster applications by
providing a single-chip solution capable of hosting real-time applications and driving a TFT display directly using an on-chip
color TFT display controller.
MPC5606S devices incorporate a cost-efficient host processor core compliant with the Power Architecture™ embedded
category. The processor is 100% user-mode compatible with the original PowerPC user instruction set architecture (UISA) and
capitalizes on the available development infrastructure of current Power Architecture
TM
devices with full support from
available software drivers, operating systems and configuration code to assist with users' implementations.
Offering high performance processing at speeds up to 64 MHz, the MPC5606S family is optimized for low power consumption
and supports a range of on-chip SRAM and internal flash memories. The 1 MB flash version (MPC5606S) features 160 KB of
on-chip graphics SRAM.
Refer to
Table 1
for specific memory and feature sets of the product family members.
This document describes the features of the MPC5606S family of microcontrollers and highlights important electrical and
physical characteristics of the devices. For functional characteristics, refer to the MPC5606S
Microcontroller Reference
Manual.
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2008. All rights reserved.
Preliminary—Subject to Change Without Notice
Table of Contents
1
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1 Device Comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.2 MPC5606S Features. . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.3 MPC5606S Series Blocks . . . . . . . . . . . . . . . . . . . . . . . .6
1.3.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .6
1.3.2 Block Summary . . . . . . . . . . . . . . . . . . . . . . . . . .7
Pinout and Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . .9
2.1 144 LQFP Package Pinout . . . . . . . . . . . . . . . . . . . . . .10
2.2 176 LQFP Package Pinout . . . . . . . . . . . . . . . . . . . . . .11
2.3 208 MAPBGA Package Pinout . . . . . . . . . . . . . . . . . . .11
2.4 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.4.1 Pad Configuration during Reset Phases . . . . . .13
2.4.2 Voltage Supply Pins. . . . . . . . . . . . . . . . . . . . . .13
2.4.3 Pad Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2.4.4 System Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2.4.5 Nexus Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
2.4.6 Functional Ports A, B, C, D, E, F, G, H, I, J, K . .18
2.4.7 Signal Details. . . . . . . . . . . . . . . . . . . . . . . . . . .36
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
3.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .39
3.1.1 Recommended Operating Conditions . . . . . . . .41
3.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .44
3.2.1 General Notes for Specifications at Maximum
Junction Temperature . . . . . . . . . . . . . . . . . . . .45
3.3 EMI (Electromagnetic Interference) Characteristics . . .47
3.4 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . .47
3.4.1 Voltage Regulator Electrical Characteristics . . .47
3.4.2 Voltage monitor electrical characteristics. . . . . .48
3.4.3 Low voltage domain power consumption. . . . . .49
3.5 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .50
3.6 I/O Pad Electrical Characteristics . . . . . . . . . . . . . . . . .50
3.6.1 I/O Pad Types . . . . . . . . . . . . . . . . . . . . . . . . . .50
3.6.2 I/O Input DC Characteristics . . . . . . . . . . . . . . 50
3.6.3 I/O Output DC Characteristics . . . . . . . . . . . . . 51
3.6.4 I/O Pad Current Specification. . . . . . . . . . . . . . 55
3.7 RESET electrical characteristics . . . . . . . . . . . . . . . . . 57
3.8 Main Oscillator Electrical Characteristics . . . . . . . . . . 59
3.9 Low Power Oscillator Electrical Characteristics. . . . . . 61
3.10 FMPLL Electrical Characteristics. . . . . . . . . . . . . . . . . 62
3.11 Main RC Oscillator Electrical Characteristics . . . . . . . 63
3.12 Low Power RC Oscillator Electrical Characteristics . . 64
3.13 Flash Memory Electrical Characteristics . . . . . . . . . . . 64
3.14 Analog to Digital Converter (ADC) Electrical Characteristics
65
3.14.1 Input Impedance and ADC Accuracy . . . . . . . . 66
3.14.2 ADC Electrical Characteristics . . . . . . . . . . . . . 70
3.15 AC Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.15.1 Pad AC Specifications . . . . . . . . . . . . . . . . . . . 72
3.16 AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.16.1 IEEE 1149.1 Interface Timing . . . . . . . . . . . . . 74
3.16.2 Nexus Debug Interface. . . . . . . . . . . . . . . . . . . 77
3.16.3 Interface to TFT LCD Panels . . . . . . . . . . . . . . 78
3.16.4 External Interrupt (IRQ) and Non-Maskable
Interrupt (NMI) Timing . . . . . . . . . . . . . . . . . . . 81
3.16.5 Enhanced Modular I/O Subsystem (eMIOS) Timing
82
3.16.6 FlexCAN Timing . . . . . . . . . . . . . . . . . . . . . . . . 82
3.16.7 Deserial Serial Peripheral Interface (DSPI) . . . 83
3.16.8 I
2
C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
3.16.9 Mechanical Outline Drawings. . . . . . . . . . . . . . 89
3.17 144 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
3.18 176 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
2
3
4
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
2
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Overview
1
1.1
..
Overview
Device Comparison
Table 1. MPC5606S Family
Feature
CPU
Execution Speed
Flash (ECC)
EEPROM Emulation Block
(ECC)
RAM (ECC)
Graphics RAM
MPU
eDMA
Display Control Unit
Parallel Data Interface
Stepper Motor Controller
Stepper Motor Stall Detect
Sound Generation
LCD Segment Driver
32 kHz External Crystal
Oscillator
Real Time Counter and
Autonomous Periodic
Interrupt
Periodic Interrupt Timer
System Watchdog Timer
System Timer Module
Timed I/O
2
Yes
Yes
64 × 6
No
No
24 KB
No
256 KB
MPC5602S
MPC5604S
e200z0h
Static - 64 MHz
512 KB
4 × 16 KB
48 KB
No
12 entry
16 channels
No
No
6 motors
Yes
Yes
64 × 6
Yes
Yes
Yes
Using eMIOS
40 × 4, 38 × 6
1
Yes
Yes
48 KB
160 KB
1 MB
MPC5606S
The following sections provide high-level descriptions of the features found on the MPC5606S.
4 ch, 32-bit
Yes
4 ch, 32-bit
8 ch, 16-bit IC/OC
16 ch, 16-bit OPWM/IC/OC
ADC
3
CAN (64 Mailboxes)
CAN Sampler
SCI
SPI
QuadSPI Serial Flash
Interface
2 × DSPI
No
1 × FlexCAN
16 channels, 10-bit
2 × FlexCAN
Yes
2 × LINFlex
2 × DSPI
No
3
4
× DSPI
Yes
2 × FlexCAN
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
3
Overview
Table 1. MPC5606S Family (continued)
Feature
I
2
C
GPIO
Debug
Package
MPC5602S
2
105
Nexus 1
144 LQFP
MPC5604S
2
105
Nexus 1
144 LQFP
MPC5606S
4
105 / 132
Nexus 2+
5
144 LQFP
6
176 LQFP
208 MAPBGA
7
1
2
3
4
5
6
7
Configuration is software-programmable
IC-Input Capture, OC-Output Compare, OPWM-Output Pulse Width Modulation
Support for external multiplexer enabling up to 23 channels
QuadSPI serial Flash controller can be optionally used as a third DSPI
Nexus2+ available on 176 LQFP as alternate pin function and on 208 MAPBGA
Not all features are available simultaneously in 144 LQFP package option
The 208-pin package is not a production package; it is available in limited quantities for tool
development only.
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
4
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Overview
1.2
•
MPC5606S Features
Single issue, 32-bit Power Architecture Book E compliant CPU core complex (e200z0h)
— Compatible with classic PowerPC instruction set
— Includes variable length encoding (VLE) instruction set for smaller code size footprint; with the encoding of
mixed 16-bit and 32-bit instructions, it is possible to achieve significant code size footprint reduction over
conventional Book E compliant code
On-chip ECC flash memory with flash controller
— Up to 1 MB primary flash—two 512 KB modules with prefetch buffer and 128-bit data access port
— 64 KB data flash—separate 4×16 KB flash block for EEPROM Emulation with prefetch buffer and 128-bit data
access port
Up to 48 KB on-chip ECC SRAM with SRAM controller
Up to 160 KB on-chip non-ECC graphics SRAM with SRAM controller
Memory protection unit (MPU) with up to 12 region descriptors and 32-byte region granularity to provide basic
memory access permission
Interrupt controller (INTC) with up to 127 peripheral interrupt sources and eight software interrupts
Two frequency-modulated phase-locked loops (FMPLLs)
— Primary FMPLL provides a 64 MHz system clock
— Auxiliary FMPLL is available for use as an alternate, modulated or non-modulated clock source to eMIOS
modules and as alternate clock to the DCU for pixel clock generation
Crossbar switch architecture enables concurrent access of peripherals, flash memory or RAM from multiple bus
masters (AMBA 2.0 v6 AHB)
16-channel enhanced direct memory access controller (eDMA) with multiple transfer request sources using a DMA
channel multiplexer
Boot assist module (BAM) for embedded boot code supports boot options including download of code via a serial link
(CAN or SPI)
Display control unit to drive TFT LCD displays. It includes processing of up to four planes that can be blended together
and offers a direct un-buffered hardware bit-blitter of up to 16 software-configurable dynamic layers in order to
drastically minimize graphic memory requirements and provide fast animations. Programmable display resolutions are
available up to WVGA.
Parallel Data Interface for digital video input
The LCD segment driver module has two software programmable configurations:
— Up to 40 front plane drivers and 4 backplane drivers
— Up to 38 frontplane drivers and 6 backplane drivers
Stepper Motor Controller module with high-current drivers for up to six instrument cluster gauges driven in full dual
H-Bridge configuration including full diagnostics for short circuit detection
Stepper motor return-to-zero and stall detection module
Sound generation and playback utilizing PWM channels and eDMA; supports monotonic and polyphonic sound
24 eMIOs channels providing up to 16 PWM and 24 input capture / output compare channels
10-bit analog-to-digital converter (ADC) with a maximum conversion time of 1μs
— 16 internal channels
— Extendable to eight multiplexed external channels
Up to three DSPI (Deserial Serial Peripheral Interface) modules for full-duplex, synchronous, communications with
external devices
QuadSPI serial flash memory controller supporting single, dual and quad modes of operation to interface to external
serial flash memory or optionally can be configured to function as another DSPI module (MPC5606S only)
Two Local Interconnect Network (LIN) controller modules capable of autonomous message handling (master),
autonomous header handling (slave mode), and UART support. Compliant with LIN protocol rev 2.1
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
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Freescale Semiconductor
Preliminary—Subject to Change Without Notice
5
