Freescale Semiconductor
Data Sheet: Advance Information
Document Number: MPC5604BC
Rev. 11.1, 10/2013
MPC5604B/C
MAPBGA–225
208 MAPBGA
15 mm
15 mm x
(17 x 17 x 1.7 mm)
QFN12
144 LQFP
##_mm_x_##mm
(20 x 20 x 1.4 mm)
MPC5604B/C
Microcontroller Data Sheet
Features
•
100 LQFP
(14 x 14 x 1.4 mm)
SOT-343R
##_mm_x_##mm
TBD
PKG-TBD
## mm x ## mm
64 LQFP
(10 x 10 x 1.4 mm)
•
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Single issue, 32-bit CPU core complex (e200z0)
— Compliant with the Power Architecture
®
embedded category
— Includes an instruction set enhancement allowing variable
length encoding (VLE) for code size footprint reduction. With
the optional encoding of mixed 16-bit and 32-bit instructions, it
is possible to achieve significant code size footprint reduction.
Up to 512 KB on-chip code flash supported with the flash controller
and ECC
64 (4 × 16) KB on-chip data flash memory with ECC
Up to 48 KB on-chip SRAM with ECC
Memory protection unit (MPU) with 8 region descriptors and 32-byte
region granularity
Interrupt controller (INTC) with 148 interrupt vectors, including 16
external interrupt sources and 18 external interrupt/wakeup sources
Frequency modulated phase-locked loop (FMPLL)
Crossbar switch architecture for concurrent access to peripherals, flash
memory, or RAM from multiple bus masters
Boot assist module (BAM) supports internal flash programming via a
serial link (CAN or SCI)
Timer supports input/output channels providing a range of 16-bit input
capture, output compare, and pulse width modulation functions
(eMIOS-lite)
10-bit analog-to-digital converter (ADC)
3 serial peripheral interface (DSPI) modules
Up to 4 serial communication interface (LINFlex) modules
Up to 6 enhanced full CAN (FlexCAN) modules with configurable
buffers
1 inter IC communication interface (I
2
C) module
Up to 123 configurable general purpose pins supporting input and
output operations (package dependent)
Real Time Counter (RTC) with clock source from 128 kHz or 16 MHz
internal RC oscillator supporting autonomous wakeup with 1 ms
resolution with max timeout of 2 seconds
Up to 6 periodic interrupt timers (PIT) with 32-bit counter resolution
1 System Module Timer (STM)
Nexus development interface (NDI) per IEEE-ISTO 5001-2003 Class
Two Plus standard
Device/board boundary Scan testing supported with per Joint Test
Action Group (JTAG) of IEEE (IEEE 1149.1)
On-chip voltage regulator (VREG) for regulation of input supply for
all internal levels
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . 8
3.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 Pad configuration during reset phases . . . . . . . . . . . . . 11
3.3 Voltage supply pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4 Pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.5 System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.6 Functional ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.7 Nexus 2+ pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 29
3.9 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.10 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . . 30
3.11 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.12 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . 32
3.13 Recommended operating conditions . . . . . . . . . . . . . . 33
3.14 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . 35
3.15 I/O pad electrical characteristics. . . . . . . . . . . . . . . . . . 36
3.16 RESET electrical characteristics . . . . . . . . . . . . . . . . . 46
3.17 Power management electrical characteristics . . . . . . . 48
3.18 Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.19 Flash memory electrical characteristics . . . . . . . . . . . . 56
3.20 Electromagnetic compatibility (EMC) characteristics . . 58
3.21 Fast external crystal oscillator (4 to 16 MHz) electrical
characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.22 Slow external crystal oscillator (32 kHz) electrical
characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.23 FMPLL electrical characteristics. . . . . . . . . . . . . . . . . . 65
3.24 Fast internal RC oscillator (16 MHz) electrical
characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.25 Slow internal RC oscillator (128 kHz) electrical
characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.26 ADC electrical characteristics. . . . . . . . . . . . . . . . . . . . 69
3.27 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
4.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . 86
5 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Appendix AAbbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
1
This document contains information on a product under development. Freescale reserves
the right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2009-2013. All rights reserved.
Introduction
1
1.1
Introduction
Document overview
This document describes the features of the family and options available within the family members, and highlights important
electrical and physical characteristics of the device. To ensure a complete understanding of the device functionality, refer also
to the device reference manual and errata sheet.
1.2
Description
The MPC5604B/C is a family of next generation microcontrollers built on the Power Architecture
®
embedded category.
The MPC5604B/C family of 32-bit microcontrollers is the latest achievement in integrated automotive application controllers.
It belongs to an expanding family of automotive-focused products designed to address the next wave of body electronics
applications within the vehicle. The advanced and cost-efficient host processor core of this automotive controller family
complies with the Power Architecture embedded category and only implements the VLE (variable-length encoding) APU,
providing improved code density. It operates at speeds of up to 64 MHz and offers high performance processing optimized for
low power consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and
is supported with software drivers, operating systems and configuration code to assist with users implementations.
MPC5604B/C Microcontroller Data Sheet, Rev. 11.1
2
Freescale Semiconductor
Table 1. MPC5604B/C device comparison
1
Introduction
Device
Feature
MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC5604
02BxLH 02BxLL 02BxLQ 02CxLH 02CxLL 03BxLH 03BxLL 03BxLQ 03CxLH 03CxLL 04BxLH 04BxLL 04BxLQ 04CxLH 04CxLL BxMG
e200z0h
Static – up to 64 MHz
256 KB
384 KB
64 KB (4 × 16 KB)
24 KB
32 KB
28 KB
8-entry
12 ch
28 ch
36 ch
8 ch
28 ch
12 ch
28 ch
36 ch
8 ch
Yes
12 ch,
16-bit
2 ch
10 ch
—
28 ch,
16-bit
5 ch
20 ch
3 ch
3
5
2
2
6
3
2
5
3
6
2
3
7
1
Yes
45
79
123
45
79
45
79
123
JTAG
64
LQFP
100
LQFP
144
LQFP
64
LQFP
100
LQFP
64
LQFP
100
LQFP
144
LQFP
64
LQFP
100
LQFP
64
LQFP
100
LQFP
144
LQFP
64
LQFP
45
79
45
79
123
45
79
123
Nexus2+
100
208
LQFP MAPBGA
9
3
2
5
56 ch,
16-bit
10 ch
40 ch
6 ch
12 ch,
16-bit
2 ch
10 ch
—
28 ch,
16-bit
5 ch
20 ch
3 ch
12 ch,
16-bit
2 ch
10 ch
—
28 ch,
16-bit
5 ch
20 ch
3 ch
56 ch,
16-bit
10 ch
40 ch
6 ch
12 ch,
16-bit
2 ch
10 ch
—
28 ch,
16-bit
5 ch
20 ch
3 ch
4
3
6
2
3
7
3
2
5
3
6
12 ch,
16-bit
2 ch
10 ch
—
28 ch,
16-bit
5 ch
20 ch
3 ch
56 ch,
16-bit
10 ch
40 ch
6 ch
12 ch,
16-bit
2 ch
10 ch
—
28 ch,
16-bit
5 ch
20 ch
3 ch
56 ch,
16-bit
10 ch
40 ch
6 ch
28 ch
12 ch
28 ch
36 ch
8 ch
28 ch
36 ch
40 KB
32 KB
48 KB
512 KB
3
CPU
Execution
speed
2
Code Flash
Data Flash
RAM
MPU
ADC (10-bit)
CTU
Total timer
I/O
3
eMIOS
• PWM + MC
+ IC/OC
4
• PWM +
IC/OC
4
• IC/OC
4
SCI (LINFlex)
SPI (DSPI)
CAN
(FlexCAN)
I
2
C
32 kHz
oscillator
GPIO
8
Debug
Package
Freescale Semiconductor
MPC5604B/C Microcontroller Data Sheet, Rev. 11.1
4
MPC5604B/C Microcontroller Data Sheet, Rev. 11.1
Freescale Semiconductor
1
2
3
4
5
6
7
8
9
Feature set dependent on selected peripheral multiplexing—table shows example implementation.
Based on 125 °C ambient operating temperature.
See the eMIOS section of the device reference manual for information on the channel configuration and functions.
IC – Input Capture; OC – Output Compare; PWM – Pulse Width Modulation; MC – Modulus counter.
SCI0, SCI1 and SCI2 are available. SCI3 is not available.
CAN0, CAN1 are available. CAN2, CAN3, CAN4 and CAN5 are not available.
CAN0, CAN1 and CAN2 are available. CAN3, CAN4 and CAN5 are not available.
I/O count based on multiplexing with peripherals.
208 MAPBGA available only as development package for Nexus2+.
Block diagram
2
Block diagram
Figure 1
shows a top-level block diagram of the MPC5604B/C device series.
Block diagram
JTAG
JTAG port
Nexus port
Nexus
NMI
SIUL
Voltage
regulator
NMI
Interrupt requests
from peripheral
blocks
INTC
Clocks
FMPLL
CMU
64-bit 2 x 3 Crossbar Switch
Instructions
e200z0h
(Master)
Data
Nexus 2+
(Master)
SRAM
48 KB
Code Flash Data Flash
512 KB
64 KB
SRAM
controller
MPU
Flash
controller
(Slave)
(Slave)
(Slave)
MPU
registers
RTC
STM
SWT
ECSM
PIT
MC_RGM MC_CGM MC_ME MC_PCU
BAM
SSCM
Peripheral bridge
Interrupt
request
SIUL
Reset control
External
interrupt
request
IMUX
GPIO and
pad control
36 Ch.
ADC
CTU
2x
eMIOS
4x
LINFlex
3x
DSPI
I
2
C
6x
FlexCAN
WKPU
I/O
Legend:
ADC
BAM
FlexCAN
CMU
CTU
DSPI
eMIOS
FMPLL
I
2
C
IMUX
INTC
JTAG
LINFlex
ECSM
MC_CGM
...
...
...
...
...
Interrupt
request with
wakeup
functionality
Analog-to-Digital Converter
Boot Assist Module
Controller Area Network
Clock Monitor Unit
Cross Triggering Unit
Deserial Serial Peripheral Interface
Enhanced Modular Input Output System
Frequency-Modulated Phase-Locked Loop
Inter-integrated Circuit Bus
Internal Multiplexer
Interrupt Controller
JTAG controller
Serial Communication Interface (LIN support)
Error Correction Status Module
Clock Generation Module
MC_ME
MC_PCU
MC_RGM
MPU
Nexus
NMI
PIT
RTC
SIUL
SRAM
SSCM
STM
SWT
WKPU
Mode Entry Module
Power Control Unit
Reset Generation Module
Memory Protection Unit
Nexus Development Interface (NDI) Level
Non-Maskable Interrupt
Periodic Interrupt Timer
Real-Time Clock
System Integration Unit Lite
Static Random-Access Memory
System Status Configuration Module
System Timer Module
Software Watchdog Timer
Wakeup Unit
Figure 1. MPC5604B/C block diagram
Table 2
summarizes the functions of all blocks present in the MPC5604B/C series of microcontrollers. Please note that the
presence and number of blocks vary by device and package.
MPC5604B/C Microcontroller Data Sheet, Rev. 11.1
Freescale Semiconductor
5
单片机
