NXP Semiconductors
Data Sheet: Technical Data
Document Number MPC5748G
Rev. 6, 11/2018
MPC5748G Microcontroller
Data Sheet
Features
• 2 x 160 MHz Power Architecture® e200Z4 Dual issue,
32-bit CPU
– Single precision floating point operations
– 8 KB instruction cache and 4 KB data cache
– Variable length encoding (VLE) for significant code
density improvements
• 1 x 80 MHz Power Architecture® e200Z2 Single issue,
32-bit CPU
– Using variable length encoding (VLE) for
significant code size footprint reduction
• End to end ECC
– All bus masters, for example, cores generate single
error correction, double error detection (SECDED)
code for every bus transaction
– SECDED covers 64-bit data and 29-bit address
• Memory interfaces
– 6 MB on-chip flash supported with the flash
controller
– 3 x flash page buffers (3 port flash controller)
– 768 KB on-chip SRAM across three RAM ports
• Clock interfaces
– 8-40 MHz external crystal (FXOSC)
– 16 MHz IRC (FIRC)
– 128 KHz IRC (SIRC)
– 32 KHz external crystal (SXOSC)
– Clock Monitor Unit (CMU)
– Frequency modulated phase-locked loop (FMPLL)
– Real Time Counter (RTC)
• 2x System Memory Protection Unit (SMPU) each with
16 region descriptors and 16-byte region granularity
• 16 Semaphores to manage access to shared resource
• Interrupt controller (INTC) capable of routing
interrupts to any CPU
• Multiple crossbar switch architecture for concurrent
access to peripherals, flash, and RAM from multiple
bus masters
• 32-channels eDMA controller with multiple transfer
request sources using DMAMUX
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
MPC5748G
• Boot Assist Flash (BAF) supports internal flash
programming via a serial link (LIN / SCI)
• Analog
– Two analog-to-digital converters (ADC), one 10-bit
and one 12-bit
– Three analogue comparators
– Cross Trigger Unit to enable synchronization of
ADC conversions with a timer event from the
eMIOS or from the PIT
• Communication
– Four Deserial Peripheral Interface (DSPI)
– Six Serial Peripheral interface (SPI)
– 18 serial communication interface (LIN) modules
– Eight enhanced FlexCAN3 with FD support
– Four inter-IC communication interface (IIC)
– One USB OTG Controller (USB_0) and One USB
SPH Controller (USB_1) with ULPI Interface.
– ENET complex (10/100 Ethernet) that supports
Multi queue with AVB support, 1588, and MII/
RMII
– 2 x ENET with L2 switch
– Secure Digital Hardware Controller (uSDHC)
– Dual-channel FlexRay Controller
• Audio
– 3 x Synchronous Audio Interface (SAI)
– Fractional clock dividers (FCD) operating in
conjunction with the SAIs
• Configurable I/O domains supporting FLEXCAN,
LINFlex, Ethernet, USB, MLB, uSDHC and general
I/O
• Supports wake-up from low power modes via the
WKPU controller
• On-chip voltage regulator (VREG)
• Debug functionality
– e200Z2 core:NDI per IEEE-ISTO 5001-2008
Class3+
– e200Z4 core(s): NDI per IEEE-ISTO 5001-2008
Class 3+
• Timer
– 16 Periodic Interrupt Timers (PITs)
– Three System Timer Module (STM)
– Four Software WatchDog Timers (SWT)
– 96 Configurable Enhanced Modular Input Output Subsystem (eMIOS) channels
• Device/board boundary Scan testing supported with per Joint Test Action Group (JTAG) of IEEE (IEEE 1149.1) and
1149.7 (cJTAG)
• Security
– Hardware Security Module (HSMv2)
– Password and Device Security (PASS and TDM) supporting advanced censorship and life-cycle management
– One Fault Collection and Control Unit (FCCU) to collect faults and issue interrupts
• Functional Safety
– ISO26262 ASIL compliance
• Multiple operating modes
– Includes enhanced low power operation
MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018
2
NXP Semiconductors
Table of Contents
1
2
3
Block diagram.................................................................................... 4
Family comparison.............................................................................4
Ordering parts.....................................................................................9
3.1
3.2
4
Determining valid orderable parts ..........................................9
Ordering Information ............................................................. 9
6.4
6.3.5
6.3.6
Flash memory AC timing specifications................... 40
Flash read wait state and address pipeline control
settings ...................................................................... 41
Communication interfaces.......................................................41
6.4.1
6.4.2
DSPI timing............................................................... 41
FlexRay electrical specifications............................... 47
6.4.2.1
6.4.2.2
6.4.2.3
6.4.2.4
6.4.3
6.4.4
6.4.5
FlexRay timing...................................... 47
TxEN......................................................48
TxD........................................................ 49
RxD........................................................50
General............................................................................................... 10
4.1
4.2
4.3
4.4
4.5
4.6
4.7
Absolute maximum ratings..................................................... 10
Recommended operating conditions....................................... 11
Voltage regulator electrical characteristics............................. 13
Voltage monitor electrical characteristics............................... 16
Supply current characteristics................................................. 18
Electrostatic discharge (ESD) characteristics......................... 21
Electromagnetic Compatibility (EMC) specifications............ 22
uSDHC specifications............................................... 51
Ethernet switching specifications.............................. 52
MediaLB (MLB) electrical specifications.................54
6.4.5.1
6.4.5.2
MLB 3-pin interface DC characteristics54
MLB 3-pin interface electrical
specifications......................................... 54
5
I/O parameters....................................................................................22
5.1
5.2
5.3
5.4
5.5
5.6
AC specifications @ 3.3 V Range...........................................22
DC electrical specifications @ 3.3V Range............................23
AC specifications @ 5 V Range..............................................24
DC electrical specifications @ 5 V Range..............................25
Reset pad electrical characteristics..........................................26
PORST electrical specifications..............................................28
6.5
6.4.7
6.4.6
USB electrical specifications.....................................56
6.4.6.1
6.4.6.2
USB electrical specifications................. 56
ULPI timing specifications.................... 56
SAI electrical specifications ..................................... 58
6
Peripheral operating requirements and behaviours............................ 28
6.1
Analog..................................................................................... 28
6.1.1
6.1.2
6.2
ADC electrical specifications.................................... 28
Analog Comparator (CMP) electrical specifications 32
Debug specifications............................................................... 60
6.5.1
6.5.2
6.5.3
6.5.4
JTAG interface timing .............................................. 60
Nexus timing............................................................. 62
WKPU/NMI timing................................................... 64
External interrupt timing (IRQ pin)...........................65
Clocks and PLL interfaces modules........................................33
6.2.1
6.2.2
6.2.3
6.2.4
Main oscillator electrical characteristics................... 33
32 kHz Oscillator electrical specifications ............... 35
16 MHz RC Oscillator electrical specifications........ 35
128 KHz Internal RC oscillator Electrical
specifications ............................................................ 36
6.2.5
PLL electrical specifications .................................... 36
9
8
7
Thermal attributes.............................................................................. 65
7.1
Thermal attributes................................................................... 65
Dimensions.........................................................................................67
8.1
Obtaining package dimensions ...............................................67
Pinouts................................................................................................68
9.1
Package pinouts and signal descriptions................................. 68
6.3
Memory interfaces...................................................................37
6.3.1
6.3.2
Flash memory program and erase specifications.......37
Flash memory Array Integrity and Margin Read
specifications............................................................. 38
6.3.3
6.3.4
Flash memory module life specifications..................39
Data retention vs program/erase cycles..................... 39
10 Reset sequence................................................................................... 68
10.1 Reset sequence duration.......................................................... 68
10.2 BAF execution duration.......................................................... 68
10.3 Reset sequence description......................................................69
11 Revision History.................................................................................71
MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018
NXP Semiconductors
3
Block diagram
1 Block diagram
System bus masters
160 MHz e200z4
160 MHz e200z4
8 KB i-cache 4 KB d-cache
SPFP-APU
E2 E-ECC
Nexus 3+
64-bit AHB
80 MHz e200z2
64-bit AHB
E2 E-ECC
Nexus 3+
uSDHC
Ethernet(ENET)
Ethernet Switch
eDMA
HS_USBSPH
MLB150
HSM
Flexray
HS_USBOTG
System
WKPU
BAF
FMPLL
RTC/API
64-bit data
E2 E-ECC
3 x DSMC
SMPU
2 x DSMC
4 x SWTs
16 x SEMA4
16 x PIT-RTI
Flash
E2 E-ECC
3 x SA-PF buffers
Triple ported
6 MB array (inc EEE)
3xRAM
E2 E-ECC
64-bit wide RAM
256 KB array
256 KB array
256 KB array
2 x MEMU
Peripheral clusters
80 ch 10-bit ADC0 64 ch 12-bit ADC1 1 x FlexCAN(PN)
(mix int and ext)
(mix int and ext)
7 x FlexCAN
4 x I
2
C
3 x eMIOS + BCTU
3 x analog
comparator (CMP)
3-core INTC
4 x DSPI
6 x SPI
DMA and
2 x chmux
1x 18 LinFlex
3 x SAI
3 x FCD
1 x CRC
Padkeeper
support
Register
protection
Peripheral
bridge
E2 E-ECC
32 KHz
SXOSC
3 x STM
PMC
16 MHz FIRC
DEBUG/
JTAG
FCCU
PASS
SSCM
MC_CGM,
MC_PCU,
MC_ME,
MC_RGM
SIUL
STCU
(MBIST/
LBIST)
CMU
TDM
LPU_CTL
Low power
unit interface
128 KHz
SIRC
8–40 MHz
FXOSC
*All FlexCANs optionally
support CAN FD
Figure 1. MPC5748G block diagram
2 Family comparison
The following table provides a summary of the different members of the MPC5748G
family and their proposed features. This information is intended to provide an
understanding of the range of functionality offered by this family. For full details of all of
the family derivatives please contact your marketing representative.
MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018
4
NXP Semiconductors
Family comparison
NOTE
All optional features (Flash memory, RAM, Peripherals) start
with lowest peripheral number (for example: STM_0) or
memory address and end at the highest available peripheral
number or memory address (for example: MPC574xC have 2
STM, ending with STM_1).
Table 1. MPC5748G Family Comparison1
Feature
CPUs
MPC5747C
e200z4
e200z2
FPU
Maximum
Operating
Frequency
2
Flash memory
EEPROM support
RAM
ECC
SMPU
DMA
10-bit ADC
12-bit ADC
SMPU_0: 12 entry, SMPU_1: 12 entry
e200z4
160MHz (z4)
80MHz (z2)
4 MB
512 KB
End to End
SMPU_0: 16 entry, SMPU_1: 16 entry
32 channels
48 Standard channels
32 External channels
16 Precision channels
16 Standard channels
32 External channels
AnalogComparator
BCTU
SWT
STM
PIT-RTI
RTC/API
Total Timer I/O
4
LINFlexD
FlexCAN
DSPI/SPI
1 M/S, 15 M
4 x DSPI
6 x SPI
Table continues on the next page...
2
2
16 channels PIT
1 channels RTI
Yes
96 channels
16-bits
1 M/S, 17 M
8 with optional CAN FD support
3
1
4
3
3
MPC5748C
e200z4
e200z2
e200z4
160MHz (z4)
80MHz (z2)
6 MB
MPC5746G
e200z4
e200z4
e200z2
e200z4
e200z4
160MHz (z4)
160MHz (z4)
80MHz (z2)
3 MB
768 KB
32 KB to 128 KB emulated
MPC5747G
e200z4
e200z4
e200z2
e200z4
e200z4
160MHz (z4)
160MHz (z4)
80MHz (z2)
4 MB
32 KB to 192 KB emulated
MPC5748G
e200z4
e200z4
e200z2
e200z4
e200z4
160MHz (z4)
160MHz (z4)
80MHz (z2)
6 MB
MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018
NXP Semiconductors
5
测试/测量
