INTEGRATED FREQUENCY
SYNTHESIZERS
I
NTEGER
P
LL
FREQUENCY
RANGE
STEP
SIZE
DC BIAS
REQUIREMENTS
Vcc1 & 2
(Volts)
CURRENT
Max.
(mA)
OUTPUT
POWER
(MHz)
(KHz)
dBm
Tolerance
(dB)
124SL
SETTLING
TIME
TYPICAL
PHASE NOISE
dBc/Hz
Offset at
10 KHz/100 KHz
197
TYPICAL
HARMONIC
SUPPRESSION
2nd
3rd
(dBc)
TYPICAL
SPURIOUS
REFERENCE
SIDEBAND
SUPPRESSION
(dBc)
198
PACKAGE
MODEL
(mSec)
41 - 60
121 - 176
139 - 196
291 - 325
291 - 310
304 - 307
376 - 383
392 - 411
400 - 750
477 - 512
490 - 525
550 - 850
565 - 595
595 - 605
630 - 730
695 - 705
25
12.5
16
50
5
25
25
25
250
25
50
25
50
25
25
25
+5/+12
+5/+12
+5/+5
+5/+5
+5/+5
+5/+5
+5/+5
+5/+5
+5/+15
+5/+5
+5/+5
+5/+15
+5/+5
+5/+5
+5/+15
+5/+5
50
40
45
45
45
35
35
35
45
45
45
45
45
35
45
35
+5
+5
0
0
+5
0
0
0
+5
0
0
0
0
0
+5
0
+2
+2
+3
+3
+1
+3
+3
+3
+3
+1
+3
+3
+3
+3
+2
+3
<15
<15
<15
<15
<50
<15
<15
<15
<5
<15
<15
<15
<15
<15
<15
<15
-100/-120
-105/-125
-95/-120
-95/-120
-100/-120
-110/-130
-110/-135
-95/-120
-95/-120
-95/-120
-110/-135
-100/-125
-95/-120
-105/-130
-100/-120
-105/-125
15
15
20
20
20
20
20
15
10
10
20
10
15
20
15
20
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
197
197
124SL
124SL
124SL
124SL
124SL
124SL
198
124SL
124SL
124SL
124SL
124SL
124SL
124SL
SPLL41SA
SPLL121SA
SPLL139SA
SPLL291SA
SPLL291SB
SPLL304SA
SPLL376SA
SPLL392SA
SPLL400SA
SPLL477SA
SPLL490SA
SPLL500SA
SPLL565SA
SPLL595SA
SPLL630SA
SPLL695SA
Θ
Θ
Θ
Θ
Θ
Θ
Θ
Φ
¥
¥
¥
¥
¥
¥
¥
COMMON SPECIFICATIONS
Output Impedance: 50 ohms
Reference Input Frequency : 5 to 40 MHz
Reference Input Voltage: >0.5 V p-p
Operating Temperature:-20
o
C to +70
o
C
Contact the factory for more stringent operating temperature range
Note:
-
External V
tune
Normally not connected
¥ - Programming Type -
Same programming as National Semiconductor LMX2320 chip
Φ
- Programming Type -
Same programming as National Semiconductor LMX2325 chip
Θ
- Programming Type -
Same programming as National Semiconductor LMX2332A chip, IF section
- Programming Type -
Same programming as Peregrine Semiconductor PE3282A fractional-N PLL chip. **
** Reference frequency must be multiple of (16 x step size)
For package outline drawings, see back pages.
PIN-OUT TABLE
RF Out
13
25
5
Vcc1 Vcc2
12
17,23,27
16
16
2
18
Clock In
1
8
11
Latch Enable
Input
4
12
12
Data In
5
10
9
F
ref
In
8
19
14
Lock Detect
Output
9
15
7
§ External
V
tune
--
33
--
Ground
2,3,14,15
All Other
All Other
Package
Style
124SL
198
197
201 McLean Boulevard • Paterson, New Jersey 07504 • Tel: (973) 881-8800 • Fax: (973) 881-8361
E-Mail: sales@synergymwave.com • World Wide Web: http://www.synergymwave.com
[ 37 ]
INTEGRATED FREQUENCY
SYNTHESIZERS
I
NTEGER
P
LL
FREQUENCY
RANGE
STEP
SIZE
DC BIAS
REQUIREMENTS
Vcc1 & 2
(Volts)
CURRENT
Max.
(mA)
OUTPUT
POWER
SETTLING
TIME
(MHz)
(KHz)
dBm
Tolerance
(dB)
(mSec)
TYPICAL
PHASE NOISE
dBc/Hz
Offset at
10 KHz/100 KHz
124SL
TYPICAL
HARMONIC
SUPPRESSION
2nd
3rd
(dBc)
TYPICAL
SPURIOUS
REFERENCE
SIDEBAND
SUPPRESSION
(dBc)
197
PACKAGE
MODEL
773
779
800
827
845
869
-
-
-
-
-
-
965
806
900
860
870
894
500
25
30
25
25
30
25
25
25
100
200
1000
25
25
+5/+12
+5/+5
+5/+5
+5/+5
+5/+5
+5/+5
+5/+5
+5/+5
+5/+5
+5/+5
+5/+18
+5/+15
+5/+5
+5/+5
40
35
45
35
35
35
35
35
45
45
50
45
35
35
0
0
+3
0
0
0
0
0
0
0
+2
+5
0
0
+1
+3
+3
+3
+3
+3
+3
+3
+3
+3
+3
+3
+3
+3
<15
<15
<15
<15
<15
<15
<15
<15
<15
<15
<10
<15
<15
<15
-95/-120
-105/-130
-100/-125
-105/-130
-105/-130
-105/-130
-105/-130
-105/-130
-95/-120
-95/-115
-92/-110
-86/-106
-105/-130
-95/-115
15
20
20
20
20
20
20
20
15
20
15
10
20
20
20
15
15
15
15
15
15
15
15
15
15
15
15
15
75
60
60
60
60
60
60
60
60
60
70
60
60
60
197
124SL
124SL
124SL
124SL
124SL
124SL
124SL
124SL
124SL
197
124SL
124SL
124SL
SPLL773SA
SPLL779SA
SPLL800SA
SPLL827SA
SPLL845SA
SPLL869SA
SPLL895SA
SPLL914SA
SPLL939SA
SPLL950SA
SPLL950SD
SPLL950SB
SPLL962SA
SPLL980SA
¤
¥
¥
¥
¥
¥
¥
¥
¥
¥
¤
Φ
¥
¥
895 - 905
914 - 941
939 - 964
950 - 1050
950 - 1450
950 - 1550
962 - 995
980 - 1005
COMMON SPECIFICATIONS
Output Impedance: 50 ohms
Reference Input Frequency : 5 to 40 MHz
Operating Temperature:-20
o
C to +70
o
C
Reference Input Voltage: >0.5 V p-p
Contact the factory for more stringent operating temperature range
Note:
¥ - Programming Type -
Same programming as National Semiconductor LMX2320 chip
Φ
- Programming Type -
Same programming as National Semiconductor LMX2325 chip
¤ - Programming Type -
Same programming as Analog Device ADF4113 PLL chip
For package outline drawings, see back pages.
PIN-OUT TABLE
RF Out
13
5
Vcc1 Vcc2
12
16
16
18
Clock In Latch Enable
Input
1
11
4
12
Data In
5
9
F
ref
In
8
14
Lock Detect
Output
9
7
Ground
2,3,14,15
All Others
Package
Style
124SL
197
201 McLean Boulevard • Paterson, New Jersey 07504 • Tel: (973) 881-8800 • Fax: (973) 881-8361
E-Mail: sales@synergymwave.com • World Wide Web: http://www.synergymwave.com
[ 38 ]
