SPT1175
8-BIT, 20 MSPS CMOS A/D CONVERTER
FEATURES
•
•
•
•
•
•
•
20 MSPS Maximum Conversion Rate
Internal Sample-and-Hold Function
90 mW Power Dissipation
Internal Voltage Reference
Single +5.0 V Power Supply
Three-State TTL-Outputs
CMOS Compatible Clock
APPLICATIONS
•
•
•
•
•
•
Video Digitizing
Image Scanners
Personal Computer Video
Medical Ultrasound
Multimedia
Digital Television
GENERAL DESCRIPTION
The SPT1175 is a CMOS two-step A/D converter capable of
digitizing full scale analog input signals into 8-bit digital words
at a sample rate of 20 MSPS.
For most applications, no external sample-and-hold or
video driving amplifiers are required due to the device's
narrow aperture time, wide bandwidth, and low input ca-
pacitance.
The SPT1175 operates from a single +5.0 V power supply
and has an internal voltage reference which eliminates the
need for external reference circuitry. All digital inputs are
CMOS compatible and the tri-state outputs are TTL-compat-
ible. The SPT1175 is ideal for most video and image pro-
cessing applications that require low power dissipation and
low cost. The SPT1175 is available in 24-lead plastic SOIC,
plastic DIP, and PLCC packages over the commercial tem-
perature range (0 to +70
°C).
It is also available in die form.
BLOCK DIAGRAM
V
RB
V
RBS
DV
DD
DGND
OE
Coarse
Sampling
Amplifier
Latch
Encoder
DØ (LSB)
D1
Error
Correction
Circuit
Data
Latches
and
3-State
Output
Buffer
D2
D3
D4
D5
D6
VIN
Reference Matrix
Fine
Sampling
Amplifier
Fine
Sampling
Amplifier
D7 (MSB)
Encoder
Analog
Mux
Latch
Timing
Generator
CLK
V
RT
V
RTS
AGND AV
D
DV
DD
AGND
Signal Processing Technologies, Inc.
4755 Forge Road, Colorado Springs, Colorado 80907, USA
Phone: (719) 528-2300 FAX: (719) 528-2370
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)
(1)
25
°
C
Supply Voltages
V
DD
........................................................... -0.5 to +7.0 V
Input Voltages
Analog Input .............................................. AGND to V
DD
Reference Input Voltage ........................... AGND to V
DD
ESD Susceptibility
(2) .................................................
±1,500
V
Temperature
Operating Temperature ................................. 0 to +70
°C
Junction Temperature ........................................... 175
°C
Lead Temperature, (soldering 10 seconds) .......... 300
°C
Storage Temperature ................................ -55 to +125
°C
Notes:
1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal
applied conditions in typical applications.
2. 100 pF discharged through a 1.5 kΩ resistor (human body model).
ELECTRICAL SPECIFICATIONS
T
A
= +25
°C,
AV
DD
=DV
DD
=+5.0 V, AGND=DGND=0.0 V, V
RB
=+0.6 V and V
RT
=+2.6 V, unless otherwise specified.
PARAMETERS
Resolution
DC Accuracy (+25
°C)
Integral Nonlinearity
Differential Nonlinearity
No Missing Codes
Analog Input
Input Voltage Range
Input Bias Current
Input Resistance
Input Capacitance
Input Bandwidth
Reference Input
Reference Ladder Resistance
Reference Current
Reference Input Voltage
Internal Bias
TEST
CONDITIONS
TEST
LEVEL
MIN
8
SPT1175
TYP
MAX
UNITS
Bits
I
I
I
I
I
VI
V
V
I
I
IV
IV
I
I
V
RB
100
12
200
5.0
0
-
0.55
1.9
±0.8
±0.6
Guaranteed
±1.2
±1.0
LSB
LSB
V
RT
±5.0
200
15
V
µA
kΩ
pF
MHz
Ω
mA
V
V
V
V
V
RB
V
RT
V
RB
V
RT
-V
RB
Short V
RT
and V
RTS
Short V
RB
and V
RBS
300
6.7
0.6
2.6
0.60
2.0
400
10.0
-
2.8
0.65
2.1
Offset Voltage Error
Top
Bottom
Timing Characteristics
Maximum Conversion Rate
Output Data Delay (td)
Output Data Delay
(Tdish, Tdisl)
Data Valid Time
(Teneh, Tenel)
Sampling Time Offset
1 MHz Input Sine Wave
(High Z)
Tri-State Circuit
I
I
I
IV
IV
IV
IV
-18
0
20
-25
10
30
18
-68
40
mV
mV
MSPS
ns
ns
ns
ns
30
100
100
5
10
NOTE: It is strongly recommended that all of the supply pins (AV
DD
, DV
DD
) be powered from the same source.
SPT
SPT1175
2
6/24/97
ELECTRICAL SPECIFICATIONS
T
A
=+25
°C,
AV
DD
=DV
DD
=+5.0 V, AGND=DGND=0.0 V, V
RB
=+0.6 V and V
RT
=+2.6 V, unless otherwise specified.
PARAMETERS
Dynamic Performance
Signal-To-Noise Ratio
f
IN
=1.0 MHz
f
IN
=3.58 MHz
f
IN
=10 MHz
Spurious Free
Dynamic Range
f
IN
=1.0 MHz
f
IN
=3.58 MHz
f
IN
=10 MHz
Differential Phase
Differential Gain
Digital Inputs
Input Current, Logic High
Input Current, Logic Low
Pulse Width High (CLK)
Pulse Width Low (CLK)
Voltage, Logic High
Voltage, Logic Low
Digital Outputs
Output Current, High
Output Current, Low
Output Current, High Z
Voltage High
Voltage Low
Power Supply Requirements
Analog Supply Voltage (AV
DD
)
Digital Supply Voltage (DV
DD
)
Supply Voltage Difference
Supply Current
Power Dissipation
TEST
CONDITIONS
f
S
= 20 MSPS
I
I
V
f
S
= 20 MSPS
I
I
V
V
V
I
I
IV
IV
I
I
IV
IV
IV
I
I
IV
IV
IV
I
I
44
41
47
44
33
0.7
1.0
1.0
1.0
15
15
4.0
1.0
-1.1
3.5
16
4.0
0.4
+4.75
+4.75
-0.1
+5.0
+5.0
0.0
18
90
+5.25
+5.25
0.1
27
135
dB
dB
dB
Degrees
%
µA
µA
ns
ns
V
V
mA
mA
µA
V
V
V
V
V
mA
mW
44
43
46
45
39
dB
dB
dB
TEST
LEVEL
MIN
SPT1175
TYP
MAX
UNITS
NTSC 20 IRE Mod Ramp
f
S
= 14.3 MSPS
V
DD
= 5.25 V, V
IH
= V
DD
V
DD
= 5.25 V, V
IL
= DGND
V
DD
= 4.75 V
V
DD
= 4.75 V
V
DD
= 5.25 V,
OE
= V
DD
(AV
DD
-DV
DD
)
f
S
=20 MSPS
TEST LEVEL CODES
All electrical characteristics are subject to the following
conditions:
All parameters having min/max specifications are guar-
anteed. The Test Level column indicates the specific
device testing actually performed during production
and Quality Assurance inspection. Any blank section in
the data column indicates that the specification is not
tested at the specified condition.
TEST LEVEL
I
II
III
IV
V
VI
TEST PROCEDURE
100% production tested at the specified temperature.
100% production tested at T
A
= +25
°C,
and sample tested
at the specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design and
characterization data.
Parameter is a typical value for information purposes only.
100% production tested at T
A
= +25
°C.
Parameter is
guaranteed over specified temperature range.
SPT
SPT1175
3
6/24/97
Table I - Output Coding
INDEX
0
1
2
....
123
124
125
....
254
255
ANALOG INPUT (V)
0.6078125
0.6078125 ~ 0.6156260
0.6156250 ~ 0.6234375
....
1.5921875 ~ 1.6000000
1.6000000 ~ 1.6078125
1.6078125 ~ 1.6156250
....
2.5843750 ~2.5921875
2.5921875 ~
DIGITAL
OUTPUT
00000000
00000001
00000010
....
01111111
10000000
10000001
....
11111110
11111111
V
RB
=0.6 V
V
RT
=2.6 V
1 LSB=7.8125 mV
Figure 1A: Timing Diagram
VIN (n)
VIN (n+1)
VIN (n+2)
VIN (n+3)
VIN
Clock
Data
Data (n-3)
Data (n-2)
Data (n-1)
Data (n)
t
d
Figure 1B: Tri-State Output Timing Diagram
50%
OE
2.5 V
220
Ω
DUT
50 pF
50%
OE
VOH
VOL
2.5 V
90%
OE
50%
90%
2.5 V
10%
TdisL
VOL
TeneL
OE
50%
90%
VOH
10%
2.5 V
TdisH
2.5 V
TeneH
SPT
SPT1175
4
6/24/97
TYPICAL INTERFACE CIRCUIT
The SPT1175 is an 8-bit analog-to-digital converter which
uses a two-step, ping-pong architecture to perform conver-
sions up to 20 MSPS. Figure 2 shows the typical interface
requirements when using the SPT1175 in normal operation.
The following sections describe the function and operation of
the device.
POWER SUPPLIES AND GROUNDING
The SPT1175 operates from a single +5 V power supply.
AV
DD
and DV
DD
must be supplied from the same source
(analog +5 V) to prevent a latch-up condition due to power
supply sequencing. Each power supply pin should be by-
passed as closely as possible to the device. For optimal
performance, both the AGND and DGND should be con-
nected to the system's analog ground plane.
ANALOG INPUT AND VOLTAGE REFERENCE
The SPT1175 input voltage range is V
RT
>V
IN
>V
RB
. Two
reference voltages (V
RT
and V
RB
) are required for device
operation. These voltages may be generated externally or
the SPT1175's internal reference may be used.
Inside the SPT1175, reference resistors are placed between
AV
DD
and V
RTS
and between AGND and V
RBS
so that V
RTS
and V
RBS
generate the 2.6 V and 0.6 V references respec-
tively. (See figure 3.) In order to utilize the internal self-bias
reference voltage, V
RTS
is to be shorted with V
RT
and the
Figure 2 - Typical Interface Circuit
10
10
10 +
10 +
+
+5
R1
2k
Q1
FB
+5 V
GND
-5
+5
+15
-15
+
GND
+15
-5
-15
+5
V
RBS
pin is to be shorted to the V
RB
pin. The self-bias internal
reference is not as stable over temperature and supply
variations as externally generated reference voltages but will
perform well in many commercial video applications.
Figure 3 - Reference Circuit Diagram
SPT1175
AVDD
5.0V
AGND
0V
DIGITAL INPUTS AND OUTPUTS
The analog input is sampled and tracked on the first 'H' cycle
of the external clock and is held from the falling edge of CLK.
The output remains valid (output hold time), and the new data
becomes valid (output delay time) after the rising edge of
CLK, delayed by 2.5 clock cycles. The clock input and output
enable input must be driven at CMOS-compatible levels.
EVALUATION BOARD
The EB1175 evaluation board is available to aid designers in
demonstrating the full performance of the SPT1175. This
board includes a reference circuit, clock driver circuit, output
data latches, and an on-board reconstruction DAC. An appli-
cation note describing the operation of the board is available.
Contact the factory for price and delivery.
VRTS
2.6 V
VRB
VRT
0.6 V
VRBS
13
14
15
DVDD
AVDD
AVDD
VRTS
VRT
AVDD
VIN
AGND
AGND
VRBS
VRB
DGND
CLK 12
DVDD 11
D7 10(MSB)
D6 9
D5 8
D4 7
D3 6
D2 5
D1 4
D0
DGND
3 (LSB)
2
Outputs
750
R9
C28
-15 +15
16
+
4
7
+5 V
D1
R37
C29
VIN
U1=Eleantec, EL2030
U2=OP.07
D1=D2=RCA, SK9091
Q1=Q2=2N2222A
FR=FairRite, 2743001111
All capacitors are 0.01 µF unless
otherwise specified.
17
18
19
D2
3
75
R35
2 _
U1
750
R36
750
20
21
_
10 k
R6
C58
R10
2
U2
3 +
C59
6 R15
10
C8
C61
22
23
24
R8
-5
750
+5
R2
R13
Q2
2k
200
7.5 k
-15
C60
-15
+15
OE 1
3-ST
EN
+5
NOTE: AVDD and DVDD must be supplied from the same source (Analog +5 V)
to prevent a latch-up condition due to power supply sequencing.
SPT
SPT1175
5
6/24/97
