SPT5510
16-BIT, 200 MWPS ECL D/A CONVERTER
FEATURES
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16-Bit, 200 MWPS digital-to-analog converter
Differential linearity of
±0.6
LSB (typical)
Integral linearity of
±0.75
LSB (typical)
Fast settling time: 35 ns to 0.0008%; 25 ns to 0.01%
Low glitch energy
On-chip voltage reference
ECL compatibility
APPLICATIONS
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High-precision arbitrary waveform generation
Test and measurement instrumentation
Digital waveform synthesis
Microwave and satellite modems
Disk drive test equipment
Industrial process control
Military applications
GENERAL DESCRIPTION
The SPT5510 is a 16-bit, 200 MWPS digital-to-analog
converter designed for high-resolution waveform synthesis
for test and measurement instrumentation applications. It
features true 16-bit linearity, with differential non-linearity of
typically
±0.6
LSB and integral non-linearity of
±0.75
LSB. It
has a very high-speed update rate of up to 200 MHz and is
ECL compatible. It has an ultrafast settling time of 25 ns to
0.01% and 35 ns to 0.0008%.
The SPT5510 operates over an industrial temperature
range of –40
°C
to +85
°C
and is available in a 10 x 10 mm,
44-lead metric quad flat pack (MQFP) plastic package.
BLOCK DIAGRAM
REF
IN
D15–D12
I
OUT
I
OUT
MSB
Decoder
16
MSB Latch
16
I
OUT
Digital Inputs
D15–D0
16
Input
Latch
LSB
Buffer
12
LSB Latch
12
Bias
D11–D0
CLK
BG
OUT
Current
Cells
I
OUT
Bandgap
Reference
Bias
R
SET
AMP
INB
+
–
Ref
Amp
Reference
Cell
20
AMP
OUT
10
AMP
CC
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)
1
Supply Voltages
Negative supply voltage (V
EE
) ................................. –7 V
A/D ground voltage differential ................................ 0.5 V
Input Voltages
Digital input voltage (D15–D0, Clock)... ........... –2.5 to 0 V
Ref amp input voltage range .......................... –2.5 to 0 V
Reference input voltage range (Ref In) ...... V
EE
to –2.5 V
Output Currents
Bandgap reference output current .....................
±500 µA
Ref amplifier output current ................................
±2.5
mA
Temperature
Operating temperature ............................... –40 to +85
°C
Junction temperature .......................................... +150
°C
Lead, soldering (10 seconds) ............................. +250
°C
Storage .................................................... –65 to +150
°C
Note:
1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for nominal operating
conditions.
ELECTRICAL SPECIFICATIONS
T
A
= 25
°C,
V
EE
=–5.2 V
±5%,
50% duty cycle clock, unless otherwise specified.
PARAMETERS
DC Performance
1
Resolution
Differential Linearity
Differential Linearity
Integral Linearity
Integral Linearity
Integral Linearity Drift
Offset Drift
Monotonicity
Output Capacitance
Gain Error
Gain Error Tempco
Gain Error Tempco
Offset Error
Compliance Voltage
Output Resistance
Dynamic Performance
Conversion Rate
Settling Time t
ST2
TEST
CONDITIONS
TEST
LEVEL
MIN
SPT5510
TYP
16
±0.6
±1.0
±0.75
±1.5
MAX
UNITS
Bits
LSB
LSB
LSB
LSB
LSB/°C
ppm FS/°C
Bits
pF
% FS
ppm FS/°C
ppm FS/°C
µA
V
kΩ
MHz
T
MIN
–T
MAX
T
MIN
–T
MAX
T
MIN
–T
MAX
With Ext Reference
With Internal Bandgap Ref
VI
IV
VI
IV
IV
IV
V
V
I
V
V
I
IV
IV
IV
–1.95
–4.0
–1.95
–4.0
–0.2
–2.5
15
–2
1.95
4.0
1.95
4.0
0.2
2.5
10
0.4
50
50
2
–4
–1.2
0.88
200
1.1
4
2
1.32
Settling to
±0.01%
Settling to
±0.0008%
Delay Time t
D
Glitch Energy
Full Scale Output Current
Rise Time/Fall Time
Spurious Free Dynamic Range
ƒ
OUT
=5 MHz; ƒ
CLOCK
=30 MHz
ƒ
OUT
=10 MHz; ƒ
CLOCK
=100 MHz
1
Measured
2
Measured
With On-Chip References
R
L
= 50
Ω
10 MHz Span
10 MHz Span
V
V
V
V
V
V
V
V
25
35
2
30
19
2
84
76
ns
ns
ns
pV-s
mA
ns
dB
dB
at 0 V output using I-V.
as voltage settling for mid-scale transition; R
L
= 50
Ω.
SPT5510
2
9/27/00
ELECTRICAL SPECIFICATIONS
T
A
= 25
°C,
V
EE
=–5.2 V
±5%,
50% duty cycle clock, unless otherwise specified.
TEST
PARAMETERS
Power Supply Requirements
Negative Supply Current (–5.2 V)
Nominal Power Dissipation
Power Supply Rejection Ratio
Voltage Input and Control
Bandgap Reference Voltage
Bandgap Output Current
Ref Amp Bandwidth
3
Ref Amp Input Current
Ref Amp Output Current
Ref In Operating Voltage
Digital Inputs
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Input Capacitance
Input Setup Time (t
S
)
Input Hold Time (t
H
)
Clock Pulse Width (t
PWH
)
3
Ref
TEST
LEVEL
VI
V
I
V
IV
V
V
V
V
VI
VI
V
V
V
IV
IV
IV
MIN
SPT5510
TYP
115
600
±0.002
–1.2
16
40
16
200
–3.4
–0.8
–1.7
2.5
0
3
MAX
150
800
0.6
UNITS
mA
mW
% FS
V
µA
MHz
µA
µA
V
V
V
µA
µA
pF
ns
ns
ns
CONDITIONS
T
MIN
–T
MAX
∆V
Supply =
±5
%
–0.6
T
A
=25
°C ±10 °C
–110
220
T
MIN
–T
MAX
T
MIN
–T
MAX
–0.8 V
–1.8 V
–1.0
–1.5
3.0
0.5
1.5
Amp Bandwidth is limited by its compensation network
TEST LEVEL CODES
All electrical characteristics are subject
to the following conditions:
All parameters having min/max specifi-
cations are guaranteed. The Test Level
column indicates the specific device
testing actually performed during pro-
duction and Quality Assurance inspec-
tion. Any blank section in the data
column indicates that the specification
is not tested at the specified condition.
TEST LEVEL
I
II
III
IV
V
VI
TEST PROCEDURE
100% production tested at the specified temperature.
100% production tested at T
A
= +25
°C,
and sample tested at the specified
temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design and characterization
data.
Parameter is a typical value for information purposes only.
100% production tested at T
A
= +25
°C.
Parameter is guaranteed over
specified temperature range.
SPT5510
3
9/27/00
THEORY OF OPERATION
The SPT5510 is a segmented 16-bit current-output DAC.
The four MSBs, D15–D12, are decoded to fifteen unit cells
(current sinks). The remaining bits (D11–D0) are binary;
bits D9–D0 are derived from an R-2R ladder. All cells are
laser trimmed for maximum accuracy. The block diagram
shows the basic architecture.
All output cells are always on, with the data determining
whether a given cell’s current is routed from I
OUT
or I
OUT
.
This provides nearly constant power dissipation indepen-
dent of data and clock rate. It also reduces noise transients
on power and ground lines.
The reference loop utilizes an MSB-weighted cell and pro-
vides a gain of about 16 to the output. The on-chip refer-
ence amplifier has very high open-loop gain and is offset
trimmed to provide a very low temperature drift (typically
<10 ppm/°C gain drift).
Figure 1 – Typical Interface Circuit
POWER SUPPLY AND GROUNDING
The SPT5510 requires a single –5.2V power supply. All
supply pins attach to a common on-chip power bus and
should be treated as analog supplies. For best settling per-
formance, each supply pin should be decoupled as shown
in figure 1 – typical interface circuit.
There are three separate on-chip ground busses. DGND
pins should be tied together and connected to system
ground through a ferrite bead. REFGND and OGND pins
should be tied directly to the SPT5510’s ground plane and
connected to system ground through a ferrite bead. It is
critical that REFGND and OGND are very tightly coupled,
as any differential signal (dc offset, noise, etc.) will be
transmitted to the output. Two of the OGND pins can be
disconnected from the ground plane and used as sense
lines for a current-to-voltage converter, as shown in the
OUTPUTS section.
C13
20 pF
C12
10 pF
.01
µF
1K
50
47 pF
47 pF
1K
AV
EE
.01
µF
C7
R7
R9
C9
C10
22
20
12
19
16
AMP
INB
18
REFGND
REFGND
BG
OUT
R
SET
CLK
17
AMP
CC
AMP
B
15
9
AMP
OUT
1
2
3
4
5
6
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
REF
IN
21
R10
50
R8
C8
I
OUT
41
Input
Data
7
8
25
26
27
28
29
30
31
32
SPT5510
36
I
OUT
OGND
OGND
OGND
DGND
OGND
DGND
DGND
DGND
AV
EE
AV
EE
AV
EE
AV
EE
AV
EE
AV
EE
AV
EE
44
10
24
33
40
42
35
37
39
43
11
R1
R2
10
R4
10
2.2
µF
2.2
µF
2.2
µF
2.2
µF
.01
µF
.01
µF
.01
µF
.01
µF
R6
10
C5
C6
.01
µF
R3
10
C14
C15
C17
C1
.01
µF
C2
C3
C16
C4
R5
10
10
C1–C13 — SURFACE MOUNT CERAMIC CHIP
C14–C17 — TANTALUM
R1–R6 — CARBON FILM 1/4 W
R7–R10 — SURFACE MOUNT CERAMIC CHIP
FB — FERRITE BEAD is to be located as closely
to the device as possible.
FB
AV
EE
13
14
23
34
38
AV
EE
C11
47 pF
Output
Output
Complementary
SPT5510
4
9/27/00
Wideband decoupling is required for optimum settling per-
formance. This may require several capacitors in parallel,
and series resistors when appropriate, to reduce resonance
effects. Some applications may need only a single capaci-
tor; however, decoupling influences both long- and short-
term settling, so caution is urged. Your application may
require some research to determine the optimum power
supply decoupling network.
DIGITAL INPUTS AND TIMING
Each digital input is buffered, decoded, and then latched
into D flip-flops which drive the output switches. Master-
slave flip-flops are not used; thus, there is only a 1/2 clock
period delay (max) from data change to output change. In
this architecture, clock and data edge speeds (i.e., rise/fall
times) may affect data feedthrough. Using a data edge of
approximately 0.8 ns will cause data feedthrough of about
10 pV-s, while a 5 ns data edge will reduce the feedthrough
to about 4 pV-s. Data lines may include series resistors or
RC filters for edge control if desired.
The clock signal controls when the data is latched into the
flip-flops. When the CLK is high, the DAC is in track mode. A
negative going CLK latches the data. If CLK is held low, the
DAC is in hold mode. See figure 2.
Figure 2 – Timing Diagram
t
S
CLK
t
H
t
D
OUTPUTS
The output is comprised of current sinks, R-2R ladder, and
associated parasitics. See figure 3 for an equivalent output
circuit.
The DAC’s full-scale output current when using the internal
reference amplifier is determined by the voltage at pin
AMP
INB
and the R
SET
resistance. It can be found (to within
an LSB) by using the following formula:
I
OUT
FS = (AMP
INB
/R
SET
) x 16
The inputs determine whether the current from each sink
comes from I
OUT
or I
OUT
as follows:
Code (D15 is MSB)
0 (zero scale)
32768 (mid-scale)
65535 (full-scale)
I
OUT
No current
I
OUT
= I
OUT
All current
I
OUT
All current
I
OUT
= I
OUT
No current
Differential outputs facilitate maximum noise rejection and
signal swing. The DAC is trimmed using a current to voltage
(I-V) converter which provides a virtual ground at the out-
puts and includes sense lines to mitigate the impact of bus
drops. Operating into a load other than a virtual ground will
introduce a slight bow at the output. This bow is related to
the current sinks’ finite output impedance and ladder
impedance.
An example circuit using an I-V converter is shown in figure
4. Note that resistor and op-amp self heating over the DAC’s
full-scale range will introduce additional temperature depen-
dence. The op-amp and feedback resistor must both have
very low tempcos if the DAC’s intrinsic gain drift is to be
maintained. A sense line helps reduce wire effects – both IR
loss and temperature drift.
Figure 4 – I-V Converter
BNC
"I
OUT
”
DATA
I
OUT
I
OUT
t
ST
t
H
= hold time
t
D
= time to output valid
t
S
= setup time
t
ST
= settling time
OGND
I
OUT
OGND
–
250
GND
Figure 3 – Equivalent Output Circuit
I
OUT
or I
OUT
AV
EE
OGND
I
OUT
1.1k
10 pF
OGND
5
+
+
–
GND
250
BNC
"I
OUT
"
SPT5510
9/27/00
