AN7750/55/60
EVALUATION BOARD
APPLICATION NOTE
FEBRUARY 6, 2002
FEATURES
•
•
•
•
1 GSPS Conversion Rate
On-Board Reconstruction DAC
On-Board Reference Circuit
Full Speed Digital Output Through a High-Speed
Connector
• Decimated Digital Data Output
• Selectable Decimation Divide by 32/64/128 Options
• On-Board Gray-to-Binary Conversion
APPLICATIONS
• Evaluation of SPT7750, SPT7755 or SPT7760 8-bit
ADCs
• Engineering System Prototype Aid
• Guide for Design of SPT7750/55/60 Interface Circuitry
• Guide for Design of SPT7750/55/60 PCB Layout
SPECIAL REQUIREMENTS
The SPT7750/55/60 devices require adequate heat
sinking and air flow for optimal performance.
GENERAL DESCRIPTION
The EB7750/55/60 evaluation board is a tool for device
characterization and demonstration of the performance of
the SPT7750, SPT7755 and SPT7760 A/D converters.
Guaranteed minimum sample rates for the devices are as
follows: 500 MSPS for the SPT7750, 750 MSPS for the
SPT7755, and 1 GSPS for the SPT7760. At these high
conversion speeds a printed circuit board is a must. Hand-
crafted breadboards simply will not work effectively at
these speeds.
Figure 1 – Block Diagram
AGND
DGND
37 Pin D-Connector
8
8
2
The EB7750/55/60 comes with the SPT7750AIK,
SPT7755AIK, or SPT7760AIK in an 80-lead MQUAD sur-
face mount package directly soldered to the board for opti-
mum performance. The EB7750/55/60 is capable of oper-
ating at clock rates up to 1 GSPS (clock rates higher than
1 GSPS are possible but not guaranteed). The block dia-
gram of the board is shown in figure 1. Note that adequate
air flow and a heat sink are necessary for optimum perfor-
mance of the ADC.
High Speed/Density
Connector (50
W)
A
B
8
8
A
AGND
HEX D-Latches
(2x SY100S351)
SPT7750/55/60
V
RT
Reference
Circuits
V
RM
V
RB
8
2:1 MUX +D F/F
(2 x SY100E167JC)
Gray-to- Binary
(2 x S307)
8
DAC OUT
BUFFER
(4 x SY100E167JC)
Latches
(100S351)
8
B
8
8
8
8
8
SPT1018
or
SPT1019
V
IN
V
OS
CLK
C
R
V
IN
DRA
DRB
sel
CLOCK
DISTRIBUTOR
+
2
100EL
07
Receiver
÷2 /÷4 SEL
SWITCH
DELAY LINE
(100E196)
7
A/B SEL
SWITCH
ADDR
(SWITCHES)
2:1 MUX
(E157)
4:1 MUX
(E157)
3
SEL
(SWITCHES)
16
EL
COUNTER
(100E137)
+A5 V A5.2 V
D2 V D4.5 V
÷16
÷32
÷64
÷2
÷4
÷8
SPT7750/55/60 ANALOG-TO-DIGITAL
CONVERTER OVERVIEW
The SPT7750 has a guaranteed minimum sample rate of
500 MSPS; the SPT7755 has a guaranteed minimum
sample rate of 750 MSPS; and the SPT7760 has a guaran-
teed minimum sample rate of 1 GSPS. Only one –5.2 V
power supply is required. Two external references are
applied across the internal reference ladder that has a
resistance of 80
Ω
typical (60
Ω
minimum).
The top reference is typically 0 V or connected to AGND
(analog ground). The device has top force and sense pins
(V
RTF
and V
RTS
) that are internally connected together.
These voltage force and sense pins can be used to mini-
mize the voltage drop across the parasitic line resistance.
The bottom reference is typically –2 V. The device also has
bottom force and sense pins (V
RBF
and V
RBS
) that are in-
ternally connected together. These can also be used to
minimize the voltage drop across the parasitic line resis-
tance.
All logic levels are compatible with both 10k ECL or 100k
ECL. It is recommended that the clock input be driven
Figure 2 – SPT7750/55/60 Timing Diagram
N
V
IN
N+1
N+2
2.0 ns
differentially (CLK and NCLK) to improve noise immunity
and reduce aperture jitter.
The digital outputs are split into two banks of 8-bit words
and an overrange bit. Each bank is updated at 1/2 of the
input clock rate and are 180° out of phase from each other.
Differential data ready signals for each bank are provided
to accurately latch each data bank into a register. The out-
put data is in a gray code format. Figure 2 shows a timing
diagram of the device and shows the input to output rela-
tionship, clock-to-output delay and output latency.
The full-scale analog input bandwidth is 500 MHz
(900 MHz for small signal bandwidth). The input capaci-
tance is 15 pF (typical) for the MQUAD package.
Power dissipation is specified at 6.25 W maximum at
+25 °C (junction temperature).
Adequate air flow and a
heat sink are necessary.
The data sheet provides the re-
quired information necessary for selection of a heat sink
and indicates the required air flow rates. Refer to the Ther-
mal Management section of the SPT7750/55/60 data
sheet.
N+5
N+4
N+3
N+6
CLK
CLK
DRA
DRA
Data Bank A
N-2
1.4 ns
typ
1.75 ns
typ
1.75 ns
typ
N
N+2
N+4
DRB
DRB
Data Bank B
N-1
1.4 ns
typ
N+1
N+3
AN7750/55/60
2
2/6/02
OPERATION AND CALIBRATION
POWER SUPPLIES AND GROUNDING
Inside the SPT7750/55/60 every circuit is biased from
AGND to V
EE
(analog), except the DGND pins. This in-
cludes the clock input circuitry. To minimize any ground
loops and to optimize performance, all interfacing circuits
must be referenced to the appropriate grounds.
The reference, analog input and clock input drivers are to
be referenced to AGND. The DGND pins, digital output
loads and all logic interfacing circuits are to be referenced
to DGND. The block diagram on page 1 indicates clearly
where the AGND and DGND are split. The AGND and
DGND are tied to each other through a ferrite bead as
close to the converter as possible.
The EB7750/55/60 requires four power supplies:
Table I – EB7750/55/60 Power Supply Requirements
Supply
–A5.2 V
–D2 V
–D4.5 V
V
OS
Voltage Range (V)
Typical Current
Min
Typ
Max
–4.95
–5.2
–5.45
1.5 A
–1.95
–2.0
–2.2
2.2 A
–4.20
–4.5
–4.8
2.1 A
–0.8
–1.0
–1.2
100 µA
Table II shows the initial setup of the board jumpers and
dip switches.
Table II – Initial Setup
Option
Jumpers
Status
J3 ............... Short
J4A ............ Short
J4B ............ Short
J5 ............... Short
J6 ............... Open
J7 ............... Open
J8 ............... Short
J9 ............... Short
Switch
Status
A/B SEL ... A or B
S0 ................... HI
S1 ................... HI
S2 ................... HI
S3 .................. LO
S4 ................... HI
S5 ................... HI
S6 .................. LO
S10 ................. HI
S11 ................. HI
S12 ................. HI
S13 ................. HI
PROCEDURE FOR VERIFYING BOARD OPERATION
The following procedure will enable verification of correct
board operation:
• Connect power supplies and generators (leave off).
• Set jumpers and dip switches to proper configurations.
• Turn on clock generator and set to 499.712 MHz and
2 V
P-P
• Turn on analog input generator and set to 3.965 MHz
and 2 V
P-P
• Turn all power supplies on and observe the 61 kHz
sine wave at the scope (64 points/period).
Refer to Beat Frequency Technique section for more detail.
Figure 3 shows the recommended power supply hook-up
for the evaluation board. Fairchild recommends that all of
the power supplies be turned on and off at the same time
via a power strip.
Figure 3 – Configuration of Power Supplies
1 V
+
5.2 V
+
2 V
+
4.5 V
DAC
OUT
Ref
Out
Generator
V
OS
AGND
V
IN
AGND A5.2V
D2V DGND
DGND D4.5V
A
IN
HP8644A
Generator
EB7750/55/60
CLK
IN
Ref
IN
CLK
HP8644A
+
REFERENCE CIRCUIT
Referring to Figure 9, D3 = 1N4730A is a 3.9 V Zener
diode. Trim pot R12 adjusts the reference voltage to the
DUT and is adjusted until –2.0 V is measured at V
RBS
. This
voltage is then buffered with U1B, which is necessary to
sink up to 33 mA through the reference ladder (based on a
2 V reference and 60
Ω
minimum ladder resistance).
The top reference is connected to AGND if J3 is installed.
The top reference may be driven externally through T
F
test
point (wrt AGND) and by removing the J3 jumper.
The SPT7750/55/60 has the reference ladder middle tap
brought out to the V
RM
pin. The voltage at V
RM
must be
centered between V
RTF
and V
RBF
. The U1A circuit is used
to provide the voltage to V
RM
and can be adjusted using
R8. This circuit forces the mid-point of the ladder to the
theoretical value ( V
RBF
– V
RTF
).
2
Scope
AN7750/55/60
3
2/6/02
A decoupling capacitor of 10 µF in parallel with 0.1 µF and
100 pF surface-mount capacitors are recommended for all
reference pins (V
RTF
, V
RM
and V
RBF
).
REFERENCE CALIBRATION PROCEDURE
The reference calibration procedure is as follows:
1.Monitor the V
RBS
test point (referenced to AGND) with
DVM and adjust R12 for –2.000 V ±5 mV.
2.Meaure T
F
and V
RBS
with respect to AGND and record
them for V
RM
calculation.
3.Monitor the RM test point with the DVM (referenced to
V – V
FT
AGND) and adjust R8 for (
FB
).
2
ANALOG INPUT
Fairchild was not able to locate an Op-Amp suitable to
drive the SPT7750/55/60. It requires a bandwidth of at
least 500 MHz and at least –50 dB of distortion. Given an
input capacitance of 15 pF (for MQUAD package), the
required peak driving current is 2πƒ
C
= 23.6 mA, for
ƒ = 250 MHz.
For AC input into the EB7750/55/60, connect the analog
input into the V
IN
SMA. C6 is socketed and is the AC input
coupling capacitor. A –1.0 V applied to the V
OS
test point
(referenced to AGND) will offset the input to meet the 0 to
–2 V input range of the ADC.
If DC input is required, inject the analog input through the
V
OS
test point and place a ground cap on the V
IN
SMA. Fig-
ure 4 shows the DC-coupled input circuit with this configu-
ration. Note: Both C6 and R7 are socketed. Remove R6.
Figure 4 – DC-Coupled Input Configuration
R7
C6
signal be symmetric about zero volts with a ±1 V
P-P
(minimum) to ±2 V
P-P
amplitude.
EB7750/55/60 CALIBRATION SUMMARY
• Hook up power supplies as shown in Figure 3.
• Refer to the initial setup section for jumper/switch
setup.
• Turn all power supplies on.
• Monitor –A2 V test point with DVM with respect to
AGND.
• Adjust R15 potentiometer for –2.00 V ±0.010 V.
• Monitor the V
RBS
test point with DVM with respect to
AGND.
• Adjust the R12 potentiometer for –2 V ±0.004 V.
• Monitor the RM test point with DVM with respect to
AGND.
• Adjust R8 potentiometer for (V
FB
–V
FT
)/2 (noting that
the additional measurements of V
RBS
and T
F
are
required.)
DIGITAL OUTPUT BUFFER AND HIGH-SPEED
CONNECTOR
The SPT7750/55/60 requires a digital output buffer directly
tied to the digital outputs. All digital outputs are pulled down
to digital –2 V (–D2 V) through 49.9
Ω
resistors.
U4 through U7 are SY100E116JCs, which are Synergy
ECLiPS Standard logic, quint line receivers with differential
I/O in PLCC packages. These, as well as all the digital logic
on the board, require a power supply voltage of –4.5
±0.3 V. The digital output buffer bank B (D0B through D8B
and DRB) of the SPT7750/55/60 is input into U4 and U5,
and output buffer bank A (D0A through D8A and DRA) is
input into U6 and U7.
All the buffered outputs (from U4 through U7) are brought
out through the P1 connector. The connector P1 is a very
high-speed, high-density, 50
Ω
controlled impedance con-
nector. AMP claims reflections at 1 GHz are less than 5%
and crosstalk with 1 ns rise times is less than 4%. The
40-pin, AMP connector P1 outline is shown in figure 5
below.
Figure 5 – P1 Connector Outline
0.050
0.950
DC
INPUT
A/D
CLOCK CIRCUIT
The clock input driver uses a 100EL16 (U2) which is con-
figured to provide the conversion of a sine wave symmetri-
cal around zero to a differential ECL output. U10 is a –2 V
regulator (from analog –5.2 V) used only for U2 output
load pulldown. Note that the clock circuits are biased from
the analog supply. This is critical to maintain the optimum
performance.
CLK and NCLK test points are provided on board. These
test points physically look like what is shown in the sche-
matic. The physical layout of the test points provides a
short ground path to the ground scope probe.
To minimize the jitter and to keep the input clock duty cycle
at 50%, Fairchild recommends that the external clock input
.200
NOTES:
1)
2)
= Ground Pins, 0.025 – 0.003 Dia Typ
= Signal Pins, 0.025 – 0.003 Dia Typ
3) All Measurements Are in Inches
Pulldown resistors (49.9
Ω)
to –2 V are required for termi-
nation on each line at the receiving end.
AN7750/55/60
4
2/6/02
The EB7750/55/60 is shipped with a one-foot, high-speed
cable with another high-speed connector for the user’s re-
ceiving end. Note that the update rate at this connector is
CLKIN/2.
The output data format on P1 is gray code. A four-bit gray
code table has been included in Table III for reference.
Table III – Gray-to-Binary Conversion
Decimal
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Binary
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Gray
0000
0001
0011
0010
0110
0111
0101
0100
1100
1101
1111
1110
1010
1011
1001
1000
U11 (Synergy SY100E196JC) is a programmable delay
line and is placed in front of this cascaded counter so that
the rising edge of the clock for U8 and U9 may be adjusted
to meet the required set-up and hold times of U8 and U9
(t
S
= 100 ps min and t
h
= 150 ps min).
SET-UP AND HOLD TIME ADJUSTMENTS
To set the proper set-up and hold time for U8 and U9 (first
decimation stage) use the following procedure:
• With a high bandwidth scope, monitor the CLK_1A or
CLK_1B test point and the /D0A test point if A/B SEL =
0, or the /D0B test point if A/B SEL = 1.
• Adjust dip switches S0 – S6 so that the required set-up
and hold times are met (t
S
= 100 ps minimum and t
h
=
150 ps minimum). Refer to Table IV, which shows the
typical propagation delays achieved out of U11 using
S0 – S6.
Table IV – Propagation Delays Out of U11
Decimal
0
1
2
4
8
16
32
64
127
Step
D6 D5 D4 D3 D2 D1 D0 Typ (pS) Delay (ps)
0 0 0 0 0 0 0 (Not Valid)
0 0 0 0 0 0 1
1390
17.5
0 0 0 0 0 1 0 1407.5
35
0 0 0 0 1 0 0
1460
70
0 0 0 1 0 0 0
1530
140
0 0 1 0 0 0 0
1670
280
0 1 0 0 0 0 0
1950
560
1 0 0 0 0 0 0
2510
1120
1 1 1 1 1 1 1
3612
DECIMATION CIRCUIT
Finding memory and a reconstruction DAC that will oper-
ate at these high speeds is difficult. Decimation enables
the user to look at a periodically subsampled portion of the
output through a divide-down scheme. The decimation
circuit schematic is found in figure 10.
The decimation function is achieved in a two-stage pro-
cess in this design to minimize the impact of the decima-
tion circuit jitter. The first stage of the two-stage design per-
forms a small divide down with very precise time slicing of
the data stream. Precise time slicing is important because
jitter, rise times and part-to-part variations are critical in
this stage of the decimation circuit. The second stage per-
forms the desired division with greatly reduced timing con-
straints. The detailed timing diagrams are shown in figures
12 and 13.
The first stage receives the data at speed and divides
down the data stream by either ÷2 or ÷4. U8 and U9
(Motorola MC100E167FN 2:1 muxes followed by D flip-
flops) are used to gate the data stream. Bank A or bank B
is selected by the A/B SEL switch (A = bank A; B =
bank B).
U12 (Synergy SY100E137JC) is an 8-bit ripple binary
down counter set up as a cascade to decimate the data
ready by 8/16/32/64 or the input clock by 16/32/64/128.
Table V – Logic Propagation Delay (pS)
Part No.
100E116
100E196
100E137
100E167
100EL11
100EL07
10E157
10E158
10S307
10S313
10S351
Min
150
1390
3575
450
190
150
220
400
200
200
Typ
300
4125
650
265
260
380
650
Max
500
3612
4800
800
340
395
550
950
1100
850
1400
U14 (Synergy SY100E157) is a quad 2:1 mux with sepa-
rate select lines. U14A is used to select the data ready
source for the first stage of decimation (U8 and U9).
Switch S10 controls the selection of either ÷2 (S10 = 0) or
÷4 (S10 = 1).
AN7750/55/60
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2/6/02
