SPT7814
10-BIT, 40 MSPS, ECL OUTPUT A/D CONVERTER
FEATURES
•
•
•
•
•
•
•
•
Monolithic 40 MSPS Converter
On-Chip Track/Hold
Bipolar
±2.0
V Analog Input
57 dB SNR @ 3.58 MHz Input
50 dB SNR @ 10.3 MHz Input
Low Power (1.3 W Typical)
5 pF Input Capacitance
ECL Outputs
APPLICATIONS
•
•
•
•
•
•
Medical Imaging
Professional Video
Radar Receivers
Instrumentation
Electronic Warfare
Digital Communications
GENERAL DESCRIPTION
The SPT7814 A/D converter is a 10-bit monolithic converter
capable of word rates of a minimum of 40 MSPS. On board
track/hold function assures excellent dynamic performance
without the need for external components. Drive require-
ment problems are minimized with an input capacitance of
only 5 pF.
Inputs and outputs are ECL to provide a higher level of noise
immunity in high speed system applications. An overrange
output signal is provided to indicate overflow conditions.
Output data format is straight binary. Power dissipation is
very low at only 1.3 watts with power supply voltages of +5.0
and -5.2 volts. The SPT7814 also provides a wide input
voltage swing of
±2.0
volts.
The SPT7814 is available in a 28-lead ceramic sidebrazed
DIP, PDIP, and die form. Commercial and industrial tempera-
ture ranges are currently offered. Contact the factory for
availability of military temperature ranges and /833 pro-
cessed units.
BLOCK DIAGRAM
Analog
Input
Coarse
A/D
4
Analog
Prescaler
T/H Amplifier
Bank
Decoding Network
Digital
Output
10
Successive Interpolation
Stage i
Successive Interpolation
Stage i+1
Successive Interpolation
Stage N
Signal Processing Technologies, Inc.
4755 Forge Road, Colorado Springs, Colorado 80907, USA
Phone: (719) 528-2300 FAX: (719) 528-2370
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)
1
25
°
C
Supply Voltages
V
CC
............................................................... -0.3 to +6 V
V
EE
............................................................... +0.3 to -6 V
Input Voltages
Analog Input ............................................... V
FB
≤V
IN
≤V
FT
V
FT
, V
FB ..............................................................
+3.0 V, -3.0 V
Reference Ladder Current ..................................... 12 mA
Output
Digital Outputs .......................................... +30 to -30 mA
Temperature
Operating Temperature .............................. -25 to +85
°C
Junction Temperature
(1) ...........................................
+175
°C
Lead Temperature, (soldering 10 seconds) ........ +300
°C
Storage Temperature ................................ -65 to +150
°C
Note:
1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal
applied conditions in typical applications.
ELECTRICAL SPECIFICATIONS
T
A
=T
min
- T
max
, V
CC
=+5.0 V, V
EE
=-5.2 V, V
IN
=±2.0 V, V
SB
=-2.0 V, V
ST
=+2.0 V, f
clock
=40 MHz, 50% clock duty cycle, unless otherwise specified.
PARAMETERS
Resolution
DC Accuracy (+25
°C)
Integral Nonlinearity
Differential Nonlinearity
No Missing Codes
Analog Input
Input Voltage Range
Input Bias Current
Input Resistance
Input Capacitance
Input Bandwidth
+FS Error
-FS Error
Reference Input
Reference Ladder Resistance
Reference Ladder Tempco
Timing Characteristics
Maximum Conversion Rate
Overvoltage Recovery Time
Pipeline Delay (Latency)
Output Delay
Aperture Delay Time
Aperture Jitter Time
Dynamic Performance
Effective Number of Bits
f
IN
=1 MHz
f
IN
=3.58 MHz
f
IN
=10.3 MHz
Typical thermal impedances:
TEST
CONDITIONS
TEST
LEVEL
SPT7814A
MIN
TYP
MAX
10
SPT7814B
MIN
TYP
MAX
10
UNITS
Bits
LSB
LSB
±
Full Scale
250 kHz Sample Rate
V
V
VI
VI
VI
VI
V
V
V
V
VI
V
VI
V
IV
V
V
V
±1.0
±0.5
Guaranteed
±2.0
30
300
5
120
±2.0
±2.0
800
0.8
±1.5
±0.75
Guaranteed
±2.0
30
300
5
120
±2.0
±2.0
800
0.8
V
IN
=0 V
60
100
60
100
3 dB Small Signal
µA
kΩ
pF
MHz
LSB
LSB
Ω
Ω/°C
MHz
ns
500
500
40
20
1
5
1
5
40
20
1
5
1
5
Clock Cycle
T
A
=+25
°C
T
A
=+25
°C
T
A
=+25
°C
ns
ns
ps-RMS
8.7
8.7
7.3
28L sidebrazed DIP:
θ
ja
= 50
°C/W,
28L plastic DIP:
θ
ja
= 50
°C/W.
8.2
8.2
6.9
Bits
Bits
Bits
SPT
SPT7814
2
3/11/97
ELECTRICAL SPECIFICATIONS
T
A
=T
min
- T
max
, V
CC
=+5.0 V, V
EE
=-5.2 V, V
IN
=±2.0 V, V
SB
=-2.0 V, V
ST
=+2.0 V, f
clock
=40 MHz, 50% clock duty cycle, unless otherwise specified.
PARAMETERS
Dynamic Performance
Signal-To-Noise Ratio
(without Harmonics)
f
IN
=1 MHz
f
IN
=3.58 MHz
f
IN
=10.3 MHz
Harmonic Distortion
f
IN
=1 MHz
f
IN
=3.58 MHz
f
IN
=10.3 MHz
Signal-to-Noise and Distortion
f
IN
=1 MHz
f
IN
=3.58 MHz
f
IN
=10.3 MHz
TEST
CONDITIONS
TEST
LEVEL
SPT7814A
MIN
TYP
MAX
SPT7814B
MIN
TYP MAX
UNITS
+25
°C
T
A
=T
min
- T
max
+25
°C
+25
°C
+25
°C
T
A
=T
min
- T
max
T
A
=T
min
- T
max
I
IV
I
IV
I
IV
I
IV
I
IV
I
IV
I
IV
I
IV
I
IV
V
V
V
VI
VI
VI
VI
IV
IV
55
53
55
53
48
45
54
51
54
51
46
45
52
49
52
49
44
43
57
55
57
55
50
47
56
53
56
53
48
47
54
54
46
67
0.2
0.5
52
50
52
50
46
43
52
49
52
49
43
41
49
46
49
46
41
40
54
52
54
52
48
45
54
51
54
51
45
43
51
51
43
67
0.2
0.7
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Degree
T
A
=T
min
- T
max
+25
°C
+25
°C
+25
°C
T
A
=T
min
- T
max
T
A
=T
min
- T
max
T
A
=T
min
- T
max
+25
°C
+25
°C
T
A
=T
min
- T
max
T
A
=T
min
- T
max
Spurious Free Dynamic Range +25
°C,
f
IN
=1 MHz
Differential Phase
+25
°C,
f
IN
=3.58 & 4.35 MHz
Differential Gain
+25
°C,
f
IN
=3.58 & 4.35 MHz
Digital Inputs
Logic 1 Voltage
Logic 0 Voltage
Maximum Input Current Low
Maximum Input Current High
Pulse Width Low (CLK)
Pulse Width High (CLK)
Digital Outputs
Logic 1 Voltage
Logic 0 Voltage
50
Ω
to -2 V
50
Ω
to -2 V
%
V
-1.5 V
+750
µA
+750
µA
ns
300 ns
V
-1.5 V
+5.25
-5.45
190
160
1.8
V
V
mA
mA
W
LSB
-1.1
-500
-500
10
10
-1.1
±200
±300
-1.5
+750
+750
300
-0.8
-1.8
-5.0
-5.2
140
115
1.3
1.0
-1.1
-500
-500
10
10
-1.1
-1.5
+5.25
-5.45
170
140
1.6
+4.75
-4.95
±200
+300
VI
VI
IV
IV
VI
VI
VI
V
-0.8
-1.8
+5.0
-5.2
140
115
1.3
1.0
Power Supply Requirements
Voltages V
CC
-V
EE
Currents I
CC
-I
EE
Power Dissipation
Outputs Open
Power Supply Rejection Ratio
(5 V
±0.25
V, -5.2 V
±2.0
V)
+4.75
-4.95
SPT
SPT7814
3
3/11/97
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions:
All parameters having min/max specifications
are guaranteed. The Test Level column indi-
cates the specific device testing actually per-
formed during production and Quality Assur-
ance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
TEST LEVEL
I
II
III
IV
V
VI
TEST PROCEDURE
100% production tested at the specified temperature.
100% production tested at T
A
=25
°C,
and sample
tested at the specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design
and characterization data.
Parameter is a typical value for information purposes
only.
100% production tested at T
A
= 25
°C.
Parameter is
guaranteed over specified temperature range.
Figure 1A: Timing Diagram
N
N+1
tpwH
CLK
tpwL
N+2
CLK
td
Data Valid
N
Data Valid
N+1
Output
Data
Figure 1B: Single Event Clock
CLK
CLK
t
d
Output
Data
Data Valid
Table I - Timing Parameters
PARAMETERS
t
d
t
pwH
t
pwL
DESCRIPTION
CLK to Data Valid Prop Delay
CLK High Pulse Width
CLK Low Pulse Width
MIN
-
10
10
TYP
5
-
-
300
-
MAX
UNITS
ns
ns
ns
SPT
SPT7814
4
3/11/97
SPECIFICATION DEFINITIONS
APERTURE DELAY
Aperture delay represents the point in time, relative to the
rising edge of the CLOCK input, that the analog input is
sampled.
APERTURE JITTER
The variations in aperture delay for successive samples.
DIFFERENTIAL GAIN (DG)
A signal consisting of a sine wave superimposed on various
DC levels is applied to the input. Differential gain is the
maximum variation in the sampled sine wave amplitudes at
these DC levels.
DIFFERENTIAL PHASE (DP)
A signal consisting of a sine wave superimposed on various
DC levels that is applied to the input. Differential phase is the
variation in the sampled sine wave phases at these DC levels.
EFFECTIVE NUMBER OF BITS (ENOB)
SINAD = 6.02N + 1.76, where N is equal to the effective
number of bits.
DIFFERENTIAL NONLINEARITY (DNL)
Error in the width of each code from its theoretical value.
(Theoretical = V
FS
/2
N
)
INTEGRAL NONLINEARITY (INL)
Linearity error refers to the deviation of each individual code
(normalized) from a straight line drawn from -Fs through +Fs.
The deviation is measured from the edge of each particular
code to the true straight line.
OUTPUT DELAY
Time between the clock's triggering edge and output data
valid.
OVERVOLTAGE RECOVERY TIME
The time required for the ADC to recover to full accuracy after
an analog input signal 125% of full scale is reduced to 50%
of the full-scale value.
SIGNAL-TO-NOISE RATIO (SNR)
The ratio of the fundamental sinusoid power to the total noise
power. Harmonics are excluded.
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
The ratio of the fundamental sinusoid power to the total noise
and distortion power.
TOTAL HARMONIC DISTORTION (THD)
The ratio of the total power of the first 64 harmonics to the
power of the measured sinusoidal signal.
SPURIOUS FREE DYNAMIC RANGE (SFDR)
The ratio of the fundamental sinusoidal amplitude to the
single largest harmonic or spurious signal.
N=
SINAD - 1.76
6.02
±
FULL-SCALE ERROR (GAIN ERROR)
Difference between measured full scale response
[(+Fs) - (-Fs)] and the theoretical response (+4 V -2 LSBs)
where the +FS (full scale) input voltage is defined as the
output transition between 1-10 and 1-11 and the -FS input
voltage is defined as the output transition between 0-00 and
0-01.
INPUT BANDWIDTH
Small signal (50 mV) bandwidth (3 dB) of analog input stage.
SPT
SPT7814
5
3/11/97
汽车电子
