SPT7864
10-BIT, 40 MSPS A/D CONVERTER
TECHNICAL DATA
NOVEMBER 20, 2001
FEATURES
• 40 MSPS maximum sample rate
• 9.5 effective number of bits at ƒ
IN
= 10 MHz and
ƒ
S
= 40 MSPS
• 2 V
P-P
full-scale input range
• Differential input 2.5 V common mode
• Internal or external voltage reference
• Common-mode voltage reference output
• +3 V / +5 V digital output logic compatibility
• +5 V analog power supply
• Sleep mode power dissipation: 55 mW
APPLICATIONS
•
•
•
•
•
Video imaging
Medical imaging
Radar receivers
IR imaging
Digital communications
GENERAL DESCRIPTION
The SPT7864 is a 10-bit, 40 MSPS analog-to-digital con-
verter with low power dissipation at only 395 mW typical at
40 MSPS with a power supply of +5.0 V. The digital outputs
are +3 V or +5 V, and are user selectable. The SPT7864
has incorporated proprietary circuit design and CMOS
processing technologies to achieve its advanced perfor-
mance. Inputs and outputs are TTL/CMOS compatible to
interface with TTL/CMOS logic systems. Output data for-
mat is offset binary.
The SPT7864 is available in a 28-lead SSOP package
over the commercial temperature range.
BLOCK DIAGRAM
V
DD
GND
Sleep
V
CM
Bandgap
Reference
EXT/INT
REF
H
REF
L
V
IN
V
IN
Bias
Cell
THA
10-BIT
40 MSPS
ADC
2
CLK, CLK
10
Data
Output
Latches
& Buffers
1
10
OR
D0D9
GND
OV
DD
Signal Processing Technologies, Inc.
4755 Forge Road, Colorado Springs, Colorado 80907, USA
Phone: 719-528-2300
Fax: 719-528-2370
Web Site: http://www.spt.com
e-mail: sales@spt.com
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur) 25 °C
Supply Voltages
V
DD
...................................................................... 6.0 V
OV
DD
.................................................................... 6.0 V
Input Voltages
Analog Input ................................. –0.3 V to V
DD
+0.7 V
CLK Input ..................................... –0.3 V to V
DD
+0.7 V
Output
Digital Outputs .............................. –0.3 V to V
DD
+0.7 V
Temperature
Operating Temperature ............................... 0 to +70 °C
Storage Temperature ............................ –65 to +150 °C
Note:
Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical
applications.
ELECTRICAL SPECIFICATIONS
T
A
=T
MIN
to T
MAX
, V
DD
=+5.0 V, ƒ
S
=40 MSPS, V
REFH
=3.0 V, V
REFL
=2.0 V, OV
DD
=3.0 V, unless otherwise specified.
PARAMETERS
Resolution
DC Accuracy
Differential Linearity Error (DLE)
Integral Linearity Error (ILE)
No Missing Codes
Analog Input
Input Voltage Range (Differential)
Input Common Mode (V
CM
)
Input Capacitance
Input Bandwidth
Common Mode Rejection Ratio (CMRR)
Timing Characteristics
Conversion Rate
Pipeline Delay (Latency)
Output Delay (t
D
)
Aperture Delay Time (t
AP
)
Aperture Jitter Time
Dynamic Performance
Effective Number of Bits (ENOB)
ƒ
IN
= 10 MHz, ƒ
CLK
= 40 MSPS
Signal-to-Noise Ratio (SNR)
ƒ
IN
= 10 MHz, ƒ
CLK
= 40 MSPS
Total Harmonic Distortion (THD)
ƒ
IN
= 10 MHz, ƒ
CLK
= 40 MSPS
Signal-to-Noise and Distortion (SINAD)
ƒ
IN
= 10 MHz, ƒ
CLK
= 40 MSPS
Spurious Free Dynamic Range (SFDR)
ƒ
IN
= 10 MHz, ƒ
CLK
= 40 MSPS
TEST
CONDITIONS
TEST
LEVEL
MIN
10
SPT7864
TYP
MAX
UNITS
Bits
@ +25 °C
full temperature
@ +25 °C
full temperature
V
V
V
V
VI
V
IV
V
V
V
VI
IV
V
V
V
±0.5
±0.75
±0.6
±1.0
Guaranteed
±1
2.5
2
50
40
6
7.5
1.5
15
LSB
LSB
LSB
LSB
2
98
3
V
V
pF
MHz
dB
MSPS
clocks
ns
ns
ps (rms)
25 °C
0 °C to +70 °C
25 °C
0 °C to +70 °C
25 °C
0 °C to +70 °C
25 °C
0 °C to +70 °C
25 °C
0 °C to +70 °C
I
IV
I
IV
I
IV
I
IV
I
IV
9.3
9.3
58
57
9.5
9.5
59
59
–71
–71
–66
–65
Bits
Bits
dB
dB
dB
dB
dB
dB
dB
dB
57
57
70
68
59
59
73
71
SPT
SPT7864
2
11/20/01
ELECTRICAL SPECIFICATIONS
T
A
=T
MIN
to T
MAX
, V
DD
=+5.0 V, ƒ
S
=40 MSPS, V
REFH
=3.0 V, V
REFL
=2.0 V, OV
DD
=3.0 V, unless otherwise specified.
PARAMETERS
Power Supply Requirements
V
DD
Voltage (Analog Supply)
OV
DD
Voltage (Output Supply)
V
DD
Current
OV
DD
Current
Power Dissipation
External Voltage Reference
Internal Voltage Reference
Sleep Mode Power Dissipation
External Voltage Reference
Internal Voltage Reference
Power Supply Rejection Ratio (PSRR)
TEST
CONDITIONS
TEST
LEVEL
IV
IV
VI
VI
VI
VI
VI
VI
V
VI
V
V
VI
VI
IV
IV
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
MIN
4.75
2.7
SPT7864
TYP
5.0
3.0/5.0
74
8
387
395
45
55
45
MAX
5.25
5.25
UNITS
V
V
mA
mA
mW
mW
mW
mW
dB
V
ppm/°C
kΩ
V
V
V
V
V
V
V
V
µA
µA
V
V
µA
µA
417
425
47
56
Internal References
Common Mode Voltage Reference (V
CM
) IO = –1 µA
Common Mode Voltage Tempco
Output Impedance (V
CM
)
(EXT/INT) = 0
Reference Low Output Voltage (V
REFL
)
Reference High Output Voltage (V
REFH
) (EXT/INT) = 0
External References
Reference Low Input Voltage Range
Reference High Input Voltage Range
Digital Outputs
Output Voltage High
Output Voltage Low
Digital Inputs
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Clock Inputs
Clock Inputs High Voltage
Clock Inputs Low Voltage
Clock Inputs High Current
Clock Inputs Low Current
(EXT/INT) = 1
(EXT/INT) = 1
IO = –2 mA
IO = 2 mA
2.4
1.95
2.95
1.7
2.7
85% OV
DD
2.5
100
2
2.0
3.0
2.0
3.0
90% OV
DD
0.2
2.6
2.05
3.05
2.3
3.3
OV
DD
0.4
80% V
DD
20% V
DD
±100
±100
2
5
0.4
±115
±115
TEST LEVEL CODES
TEST LEVEL
I
II
III
IV
V
VI
TEST PROCEDURE
100% production tested at the specified temperature.
100% production tested at T
A
= +25 °C, and sample tested
at the specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design and
characterization data.
Parameter is a typical value for information purposes only.
100% production tested at T
A
= +25 °C. Parameter is
guaranteed over specified temperature range.
All electrical characteristics are subject to the
following conditions:
All parameters having min/max specifications are
guaranteed. The Test Level column indicates the
specific device testing actually performed during
production and Quality Assurance inspection. Any
blank section in the data column indicates that the
specification is not tested at the specified
condition.
SPT
SPT7864
3
11/20/01
TYPICAL PERFORMANCE CHARACTERISTICS
DLE Versus Sample Rate
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
30
ILE Versus Sample Rate
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
30
LSB
40
Sample Rate (MSPS)
50
60
70
LSB
IN
= 1 kHz
IN
= 1 kHz
40
Sample Rate (MSPS)
50
60
70
DLE Versus Temperature
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
20
ILE Versus Temperature
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
20
IN
= 1 kHz
S
= 40 MSPS
IN
= 1 kHz
S
= 40 MSPS
LSB
LSB
0
Temperature (Degrees C)
20
40
60
80
0
Temperature (Degrees C)
20
40
60
80
SNR, SINAD, –THD, SFDR Versus Sample Rate
80
IN
= 10 MHz
SFDR
THD
65
60
55
50
45
SNR
SINAD
SNR, SINAD, –THD, SFDR Versus Temperature
80
SFDR
SNR, SINAD, THD, SFDR (dB)
SNR, SINAD, THD, SFDR (dB)
75
70
75
70
65
60
55
50
45
20
SNR
SINAD
S
= 40 MHz
IN
= 10 MHz
THD
25
30
35
40
45
50
55
60
0
20
Sample Rate (MSPS)
40
60
80
Temperature (Degrees C)
SPT
SPT7864
4
11/20/01
Figure 1 – Typical Interface Circuit
T1
0.1
+
10
V
CM
V
IN
R
T1
50
W
Ext
+A5
+
10
0.1
+
10
0.1
A
IN
SPT7864
V
IN
OGND
OV
DD
GND
CLK
0.1
0.1
R
T2
50
W
CLK
V
DD
Mini-Circuits
T16T or
T11T
EXT/INT
REF
L
REF
H
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
(MSB)
(LSB)
+D3/5
50
W
Buffer
+ 10
+ 10
+A5
+A3/5
AGND
AGND
0.1
10
+D3/5
DGND
+
Ferrite Bead
+A5
T2
CLK
IN
TYPICAL INTERFACE CIRCUIT
REFERENCES
The SPT7864 has a differential analog input. The input
range is determined by the voltages V
IN
and V
IN
applied to
reference pins REF
H
and REF
L
respectively, and is equal
to ±(V
IN
–V
IN
). Externally generated reference voltages
connected to REF
H
and REF
L
should be symmetric
around 2.5 V. The input range can be defined between
±0.6 V and ±1.5 V. An internal reference exists, providing
reference voltages at pins REF
H
and REF
L
equal to +3.0 V
(V
REFH
) and +2.0 V (V
REFL
). These can be connected to
REF
H
and REF
L
by connecting pin EXT/
INT
to GND. The
references should be bypassed as close to the converter
pins as possible using 100 nF capacitors in parallel with
smaller capacitors (e.g. 220 pF) to ground.
ANALOG INPUT
The input of the SPT7864 can be configured in various
ways, dependent upon whether a single-ended or differen-
tial, AC- or DC-coupled input is wanted.
AC-coupled input is most conveniently implemented using
a transformer with a center-tapped secondary winding.
The center tap is connected to the V
CM
node, as shown in
figure 1. In order to obtain low distortion, it is important that
the selected transformer does not exhibit core saturation
at full scale. Excellent results are obtained with the Mini-
Circuits T1-6T or T1-1T. Proper termination of the input is
important for input signal purity. A small capacitor (typically
68 pF) across the inputs attenuates kickback noise from
the sample-and-hold. A small capacitor (1 nF) between
V
CM
and ground has also been proven to be advanta-
geous.
If a DC-coupled, single-ended input is wanted, a solution
based on operational amplifiers, as shown in figure 2, is
usually preferred. The AD8138 is suggested for low distor-
tion and video bandwidth. Lower cost operational amplifi-
ers may be used if the demands are less strict.
Figure 2 – DC-Coupled, Single-Ended to Differential
Conversion
(power supplies and bypassing
not shown)
51
W
470
W
Input
Offset
Analog
In
AD8138
470
W
100
W
AD8138
Mini-Circuits
T16T or
T11T
1 kW
1 kW
51
W
15 pF
100
W
51
W
470
W
470
W
AD8138
51
W
470
W
SPT
SPT7864
5
11/20/01
Logic Interface Circuit
ADC
V
IN
V
IN
Sleep
Sleep
OR
