SPT9101
125 MSPS SAMPLE-AND-HOLD AMPLIFIER
FEATURES
•
•
•
•
Second Source of AD9101
350 MHz Sampling Bandwidth
125 MHz Sampling Rate
Excellent Hold Mode Distortion
-75 dB at 50 MSPS (23 MHz V
IN
)
-62 dB at 100 MSPS (48 MHz V
IN
)
7 ns Acquisition Time to 0.1%
<1 ps Aperture Jitter
66 dB Feedthrough Rejection at 50 MHz
Low Spectral Noise Density
APPLICATIONS
•
•
•
•
•
•
Test Instrumentation Equipment
RF Demodulation Systems
High Performance CCD Capture
Digital Sampling Oscilloscopes
Commercial and Military Radar
High-Speed DAC Deglitching
•
•
•
•
GENERAL DESCRIPTION
The SPT9101 is a high-speed track-and-hold amplifier de-
signed for a wide range of use. The SPT9101 is capable of
sampling at speeds up to 125 MSPS with resolutions ranging
from 8 to 12 bits. Trim programmable internal hold and
compensation capacitors provide for optimized input band-
width and slew rate versus noise performance.
The performance of this device makes it an excellent front
end driver for a wide range of ADCs on the market today.
Significant improvements in dynamic performance can be
achieved by using this device ahead of virtually all ADCs that
do not have an internal track-and-hold.
The SPT9101 is offered in 20-lead SOIC and LCC packages
over the industrial temperature range and in die form. Contact
the factory for military and /833 package options.
BLOCK DIAGRAM
VIn
-
Sampler
+
CH
OLD
+ 4X
Amp
-
VO
UT
R
3R
CLK NCLK
RTN
Signal Processing Technologies, Inc.
4755 Forge Road, Colorado Springs, Colorado 80907, USA
Phone: (719) 528-2300 FAX: (719) 528-2370 Website: http://www.spt.com E-Mail: sales@spt.com
ABSOLUTE MAXIMUM RATING (Beyond which damage may occur)
1
Supply Voltages
Supply Voltage (+V
S
) ................................ -0.5 V to +6 V
Supply Voltage (-V
S
) ................................. -6 V to +0.5 V
Input Voltages
Analog Input Voltage ................................................
±5
V
CLK, NCLK Input ....................................... -5 V to +0.5 V
Output Currents
Continuous Output Current ................................... 70 mA
Temperature
Operating Temperature .............................. -40 to +85
°C
Junction Temperature ......................................... +150
°C
Lead, Soldering (10 seconds) ............................. +220
°C
Storage ..................................................... -65 to +150
°C
Note 1: Operation at any Absolute Maximum Ratings is not implied. See Electrical Specifications for proper nominal
applied conditions in typical application.
ELECTRICAL SPECIFICATIONS
+V
S
=+5.0 V, -V
S
=-5.2 V, R
LOAD
=100
Ω,
unless otherwise specified.
PARAMETERS
DC Performance
Gain
∆V
IN
= 0.5 V
Offset
∆V
IN
= 0 V
Output Resistance
Output Short Circuit Current
PSRR
∆V
S
= 0.5 V p-p
Pedestal Sensitivity to Pos. Supply
∆V
S
= 0.5 V p-p
Pedestal Sensitivity to Neg. Supply
∆V
S
= 0.5 V p-p
Analog Input/Output
Maximum Output Voltage Range
6
Input Bias Current
Input Capacitance
Input Resistance
Clock Inputs
Input Bias Current
Input Low Voltage
Input High Voltage
Track Mode Dynamics
TEST
CONDITIONS
+25
°C
Full Temp.
+25
°C
Full Temp.
+25
°C
Full Temp.
+25
°C
Full Temp.
Full Temp.
TEST
LEVEL
I
VI
I
VI
V
V
VI
V
V
MIN
3.93
3.9
SPT9101
TYP
4.0
±3
0.5
±60
43
4
8
MAX
4.07
4.1
±10
±30
UNITS
V/V
V/V
mV
mV
Ω
mA
dB
mV/V
mV/V
37
Full Temp.
+25
°C
Full Temp.
+25
°C
Full Temp.
+25
°C
Full Temp.
Full Temp.
VI
I
VI
V
VI
VI
VI
VI
IV
IV
V
V
V
±2.4
±2.7
±15
2
450
3
-1.8
-0.8
180
1400
55
270
3.9
±30
±35
100
V
µA
µA
pF
kΩ
µA
V
V
MHz
V/µs
ns
µV
nV
Hz
30
-1.5
-1.0
150
1100
Bandwidth (-3 dB) V
Out
= 1.0 V p-p Full Temp.
Slew Rate 4 V Output Step
Full Temp.
Overdrive Recovery Time
1
To 0.1%
Integrated Output Noise
BW = 5 to 200 MHz
Input RMS Spectral Noise
10 MHz
SPT
SPT9101
2
12/30/99
ELECTRICAL SPECIFICATIONS
+V
S
=+5.0 V, -V
S
=-5.2 V, R
LOAD
=100
Ω,
unless otherwise specified.
PARAMETERS
Hold Mode Dynamics
Worst Harmonic
V
Out
= 2 V p-p
Worst Harmonic
V
Out
= 2 V p-p
Worst Harmonic
V
Out
= 2 V p-p
Worst Harmonic
V
Out
= 2 V p-p
Sampling Bandwidth
2
V
IN
= 0.5 V p-p
Hold Noise
3
(RMS)
Droop Rate
Feedthrough Rejection (50 MHz)
V
Out
= 2 V p-p
Maximum Hold Time, V
IN
=0 V
Track-and-Hold Switching
Aperture Delay
Aperture Jitter
Pedestal Offset, V
IN
=0 V
Transient Amplitude
Settling Time to 4 mV
Glitch Product
4
V
IN
= 0 V
Hold-to-Track Switching
Acquisition Time to 0.1%
2 V Output Step
Acquisition Time to 0.01%
2 V Output Step
Power Supply
5
+V
S
Voltage
-V
S
Voltage
Power Dissipation
TEST
CONDITIONS
23 MHz, 50 MSPS
+25
°C
48 MHz, 100 MSPS
+25
°C
48 MHz, 100 MSPS
Full Temp.
48 MHz, 125 MSPS
+25
°C
-3 dB, +25 ˚C
+25
°C
V
IN
=0.0 V, +25
°C
Full Temp.
Full Temp.
+25
°C
+25
°C
+25
°C
Full Temp.
V
IN
= 0 V, Full Temp.
Full Temp.
+25
°C
TEST
LEVEL
V
IV
IV
V
V
V
V
V
IV
V
V
I
VI
V
V
V
SPT9101
MIN
TYP
-75
-62
MAX
UNITS
dB FS
-57
-53
dB FS
dB FS
dB FS
MHz
mV/s
mV/µs
dB
ns
ps
ps rms
mV
mV
mV
ns
pV-s
-57
350
150 x t
H
-40
-66
100
200
-250
<1
±10
8
4
20
±25
±35
+25
°C
+25
°C
Full Temp.
Full Temp, Track Mode
Full Temp, Clocked Mode
Full Temp, Track Mode
Full Temp, Clocked Mode
Full Temp, Track Mode
Full Temp, Clocked Mode
V
IV
IV
VI
VI
VI
VI
VI
VI
7
11
14
16
65
55
65
55
663
561
ns
ns
ns
mA
mA
mA
mA
mW
mW
54
44
54
44
551
449
1
Time to recover within rated error band from 160% overdrive.
2
Sampling bandwidth is defined as the -3 dB frequency response of the input sampler to the hold capacitor when operating in the
sampling mode. It is greater than tracking bandwidth because it does not include the bandwidth of the output amplifier.
3
Hold mode noise is proportional to the length of time a signal is held. For example, if the hold time (t
H
) is 20 ns, the accumulated
noise is typically 3
µV
(150 mV/s x 20 ns). This value must be combined with the track mode noise to obtain total noise.
Typical thermal impedances:
4
Total energy of worst case track-to-hold or hold-to-track glitch.
ΘJC
(LCC) = +6
°C/W
ΘJA
(SOIC) = +85
°C/W
in still air at +25
°C
ambient.
5
Clocked mode is specified with a 50% clock duty cycle.
6
Analog input voltage should be limited
≤0.8
volts to maintain device in linear range.
SPT
SPT9101
3
12/30/99
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions: All parameters having min/
max specifications are guaranteed. The Test
Level column indicates the specific device test-
ing actually performed during production and
Quality Assurance inspection. Any blank sec-
tion in the data column indicates that the speci-
fication is not tested at the specified condition.
TEST LEVEL
I
II
III
IV
V
VI
TEST PROCEDURE
100% production tested at the specified temperature.
100% production tested at T
A
=25
°C,
and sample
tested at the specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design
and characterization data.
Parameter is a typical value for information purposes
only.
100% production tested at T
A
= 25
°C.
Parameter is
guaranteed over specified temperature range.
Figure 1 - Timing Diagram
Input
Acquisition
Time
Observed at
Hold Capacitor
Aperature
Delay
Output
Observed at
Amplifier Output
Track-to-Hold
Settling
CLK
Hold
Track
Hold
NCLK
TIMING SPECIFICATION DEFINITIONS
ACQUISITION TIME
This is the time it takes the SPT9101 to acquire the analog
signal at the internal hold capacitor when it makes a transition
from hold mode to track mode. (See figure 1.) The acquisition
time is measured from the 50% input clock transition point to
the point when the signal is within a specified error band at the
internal hold capacitor (ahead of the output amplifier). It does
not include the delay and settling time of the output amplifier.
Because the signal is internally acquired and settled at the
hold capacitor before the output voltage has settled, the
sampler can be put in hold mode before the output has settled.
TRACK-TO-HOLD SETTLING TIME
The time required for the output to settle to within 4 mV of its
final value.
APERTURE DELAY
The aperture delay time is the interval between the leading
edge transition of the clock input and the instant when the
input signal was equal to the held value. It is the difference
in time between the digital hold switch delay and the analog
signal propagation time. Because the analog propagation
time is longer than the digital delay in the SPT9101, the
aperture delay is a negative value.
SPT
SPT9101
4
12/30/99
Figure 2 - Typical Interface Circuit
+
+A5
12
13
17
18
4
5
8
9
2.2 µF
-A5.2
+
2.2 µF
NOTES:
1) Vt = Threshold voltage:
a) For TTL or CMOS Clock input
+A5
+VS
+VS
+VS
-VS
-VS
+VS
-VS
-VS
3k
1k
VIN
15
VIN
SPT9101
RTN
1,2
CLK NCLK
10
11
GND
VOUT
18
Vt
b) For ECL Clock input
VOUT
-A5.2
3k
Vt
1k
6,7,16
2) Unless otherwise specified, all capacitors
are 0.01 or 0.1 µF, surface mount.
3)
X
= Termination (if required).
+A5
-A5.2
330
-A5.2
330
-A5.2
4) CLKIN
a) TTL/CMOS
CLKIN
R
R
96850
2
3
220
VCC
8
VEE
GND
1,16
11
220
CLK IN
Vt
X
4
IN+
SPT, HCMP96850
IN-
LE
6
12
b) ECL: Direct Input
THEORY OF OPERATION
The SPT9101 is a monolithic 125 MSPS track and hold
amplifier built on a very high-speed complementary bipolar
process. It is pin and functionally compatible with the AD9101.
It is a two stage design with a sampler driving a hold capacitor
followed by a noninverting output buffer amplifier with gain of
4. The first stage sampler is based on a current amplifier in
noninverting gain of one configuration with inverting input
connected to the output. The hold switch is integrated into this
closed-loop first stage amplifier.
The output buffer amplifier is in a noninverting gain of 4
configuration with inverting input connected to a resistor
divider driven from the output. The noninverting input from the
hold capacitor employs input bias current cancellation which
results in excellent droop rate performance. The sampler and
amplifier stages both employ complementary current ampli-
fiers for high-speed, low-distortion performance.
CLOCK DRIVER CIRCUIT (CLK, NCLK PINS)
SPT highly recommends that a differential ECL clock be used
to drive the SPT9101. Both the 10KH and 100KH family of
ECL logic can be used. The typical interface diagram, figure
2, shows the use of a SPT HCMP96850 high-speed com-
parator. The comparator has a typical propagation delay of
2.4 ns, very low offset of 3 mV, and a minimum tracking
bandwidth of 300 MHz. The comparator shown has been set
up in a feedthrough operation mode with latch enable con-
nected to a logic high.
The threshold voltage (V
t
) can be set using a resistor divider
as shown in note 1 of figure 2. The configuration shown in
note 1a is for a TTL/CMOS clock input and the configuration
shown in note 1b is for an ECL clock input. The differential
output of the comparator is directly fed to the SPT9101 clock
input. The comparator can also be driven with a sinewave
input, with the threshold voltage (V
t
) adjusted to produce the
desired track/hold duty cycle ratio.
Note 4a shows the resistor divider configuration for a TTL/
CMOS clock input. If an ECL clock is used it can be directly
fed into the comparator.
OUTPUT LEVEL SHIFTING (RTN PIN)
The RTN pin is tied to the output buffer amplifier internal
feedback resistor network as shown in the block diagram.
Normally this pin is tied to ground for a 4x gain output amplifier
configuration. However, this pin may be configured in other
ways as long as certain guidelines are met.
TYPICAL INTERFACE CIRCUIT
BOOTSTRAP CAPACITOR
The SPT9101 does not require the bootstrap capacitor that is
required on the AD9101 between pins 3 and 19. Because
pins 3 and 19 are No Connects on the SPT9101, it will work
well in existing AD9101 sockets.
SPT
SPT9101
5
12/30/99
