SST26VF016B
2.5V/3.0V 16 Mbit Serial Quad I/O (SQI) Flash Memory
Features
• Single Voltage Read and Write Operations
- 2.7-3.6V or 2.3-3.6V
• Serial Interface Architecture
- Nibble-wide multiplexed I/O’s with SPI-like serial
command structure
- Mode 0 and Mode 3
- x1/x2/x4 Serial Peripheral Interface (SPI) Protocol
• High Speed Clock Frequency
- 2.7-3.6V: 104 MHz max
- 2.3-3.6V: 80 MHz max
• Burst Modes
- Continuous linear burst
- 8/16/32/64 Byte linear burst with wrap-around
• Superior Reliability
- Endurance: 100,000 Cycles (min)
- Greater than 100 years Data Retention
• Low Power Consumption:
- Active Read current: 15 mA (typical @ 104 MHz)
- Standby Current: 15 µA (typical)
• Fast Erase Time
- Sector/Block Erase: 18 ms (typ), 25 ms (max)
- Chip Erase: 35 ms (typ), 50 ms (max)
• Page-Program
- 256 Bytes per page in x1 or x4 mode
• End-of-Write Detection
- Software polling the BUSY bit in status register
• Flexible Erase Capability
- Uniform 4 KByte sectors
- Four 8 KByte top and bottom parameter overlay
blocks
- One 32 KByte top and bottom overlay blocks
- Uniform 64 KByte overlay blocks
• Write-Suspend
- Suspend Program or Erase operation to access
another block/sector
• Software Reset (RST) mode
• Software Write Protection
- Individual-Block Write Protection with permanent
lock-down capability
- 64 KByte blocks, two 32 KByte blocks, and
eight 8 KByte parameter blocks
- Read Protection on top and bottom 8 KByte
parameter blocks
• Security ID
- One-Time Programmable (OTP) 2 KByte,
Secure ID
- 64 bit unique, factory pre-programmed
identifier
- User-programmable area
• Temperature Range
- Industrial: -40°C to +85°C
- Extended: -40°C to +105°C
• Automotive AECQ-100 Grade 2 and Grade 3
• Packages Available
- 8-contact WDFN (6mm x 5mm)
- 8-lead SOIJ (5.28 mm)
- 8-lead SOIC (3.90 mm)
• All devices are RoHS compliant
Product Description
The Serial Quad I/O™ (SQI™) family of flash-memory
devices features a six-wire, 4-bit I/O interface that
allows for low-power, high-performance operation in a
low pin-count package. SST26VF016B also supports
full command-set compatibility to traditional Serial
Peripheral Interface (SPI) protocol. System designs
using SQI flash devices occupy less board space and
ultimately lower system costs.
All members of the 26 Series, SQI family are manufac-
tured with proprietary, high-performance CMOS Super-
Flash® technology. The split-gate cell design and thick-
oxide tunneling injector attain better reliability and man-
ufacturability compared with alternate approaches.
SST26VF016B significantly improves performance and
reliability, while lowering power consumption. These
devices write (Program or Erase) with a single power
supply of 2.3-3.6V. The total energy consumed is a
function of the applied voltage, current, and time of
application. Since for any given voltage range, the
SuperFlash technology uses less current to program
and has a shorter erase time, the total energy con-
sumed during any Erase or Program operation is less
than alternative flash memory technologies.
SST26VF016B is offered in 8-contact WDFN (6 mm x
5 mm), 8-lead SOIJ (5.28 mm), and 8-lead SOIC
(3.90 mm). See Figures
2-1
through
2-3
for pin assign-
ments.
2014-2017 Microchip Technology Inc.
DS20005262D-page 1
SST26VF016B
TO OUR VALUED CUSTOMERS
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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The
last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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DS20005262D-page 2
2014-2017 Microchip Technology Inc.
SST26VF016B
1.0
BLOCK DIAGRAM
FUNCTIONAL BLOCK DIAGRAM
FIGURE 1-1:
OTP
Address
Buffers
and
Latches
X - Decoder
SuperFlash
Memory
Y - Decoder
Control Logic
Page Buffer,
I/O Buffers
and
Data Latches
Serial Interface
WP# HOLD# SCK
CE#
SIO [3:0]
20005262 B1.0
2014-2017 Microchip Technology Inc.
DS20005262D-page 3
SST26VF016B
2.0
PIN DESCRIPTION
PIN DESCRIPTION FOR
8-LEAD SOIJ
1
2
8
7
FIGURE 2-1:
FIGURE 2-3:
CE#
PIN DESCRIPTION FOR 8-
LEAD SOIC
1
8
VDD
HOLD/SIO3
SCK
SI/SIO0
CE#
SO/SIO1
WP#/SIO2
VSS
VDD
HOLD/SIO3
SCK
SI/SIO0
SO/SIO1
WP#/SIO2
VSS
2
7
Top View
3
6
Top View
3
4
6
5
4
5
20005262 08-soij S2A P1.0
20005262 08-soic SA P1.0
FIGURE 2-2:
PIN DESCRIPTION FOR
8-CONTACT WDFN
1
8
CE#
SO/SIO1
WP#/SIO2
VSS
VDD
HOLD/SIO3
SCK
SI/SIO0
2
7
Top View
3
6
4
5
20005262 08-wson QA P1.0
TABLE 2-1:
Symbol
SCK
PIN DESCRIPTION
Pin Name
Serial Clock
Functions
To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock
input, while output data is shifted out on the falling edge of the clock input.
To transfer commands, addresses, or data serially into the device or data out of
the device. Inputs are latched on the rising edge of the serial clock. Data is
shifted out on the falling edge of the serial clock. The Enable Quad I/O (EQIO)
command instruction configures these pins for Quad I/O mode.
To transfer commands, addresses or data serially into the device. Inputs are
latched on the rising edge of the serial clock. SI is the default state after a power
on reset.
To transfer data serially out of the device. Data is shifted out on the falling edge
of the serial clock. SO is the default state after a power on reset.
The device is enabled by a high to low transition on CE#. CE# must remain low
for the duration of any command sequence; or in the case of Write operations,
for the command/data input sequence.
The WP# is used in conjunction with the WPEN and IOC bits in the Configura-
tion register to prohibit write operations to the Block-Protection register. This pin
only works in SPI, single-bit and dual-bit Read mode.
Temporarily stops serial communication with the SPI Flash memory while the
device is selected. This pin only works in SPI, single-bit and dual-bit Read mode
and must be tied high when not in use.
To provide power supply voltage.
SIO[3:0]
Serial Data
Input/Output
SI
Serial Data Input
for SPI mode
Serial Data Output
for SPI mode
Chip Enable
SO
CE#
WP#
Write Protect
HOLD#
Hold
V
DD
V
SS
Power Supply
Ground
DS20005262D-page 4
2014-2017 Microchip Technology Inc.
SST26VF016B
3.0
MEMORY ORGANIZATION
The SST26VF016B SQI memory array is organized in
uniform, 4 KByte erasable sectors with the following
erasable blocks: eight 8 KByte parameter, two 32
KByte overlay, and thirty 64 KByte overlay blocks. See
Figure 3-1.
FIGURE 3-1:
MEMORY MAP
Top of Memory Block
8 KByte
8 KByte
8 KByte
8 KByte
32 KByte
64 KByte
2 Sectors for 8 KByte blocks
8 Sectors for 32 KByte blocks
16 Sectors for 64 KByte blocks
4 KByte
4 KByte
4 KByte
4 KByte
64 KByte
32 KByte
8 KByte
8 KByte
8 KByte
8 KByte
Bottom of Memory Block
20005262 F41.0
2014-2017 Microchip Technology Inc.
...
64 KByte
...
DS20005262D-page 5
