SST26VF032B / SST26VF032BA
2.5V/3.0V 32 Mbit Serial Quad I/O (SQI) Flash Memory
Features
• Single Voltage Read and Write Operations
- 2.7-3.6V or 2.3-3.6V
• Serial Interface Architecture
- Nibble-wide multiplexed I/O’s with SPI-like serial
command structure
- Mode 0 and Mode 3
- x1/x2/x4 Serial Peripheral Interface (SPI) Protocol
• High Speed Clock Frequency
- 2.7-3.6V: 104 MHz max
- 2.3-3.6V: 80 MHz max
• Burst Modes
- Continuous linear burst
- 8/16/32/64 Byte linear burst with wrap-around
• Superior Reliability
- Endurance: 100,000 Cycles (min)
- Greater than 100 years Data Retention
• Low Power Consumption:
- Active Read current: 15 mA (typical @ 104 MHz)
- Standby Current: 15 µA (typical)
• Fast Erase Time
- Sector/Block Erase: 18 ms (typ), 25 ms (max)
- Chip Erase: 35 ms (typ), 50 ms (max)
• Page-Program
- 256 Bytes per page in x1 or x4 mode
• End-of-Write Detection
- Software polling the BUSY bit in status register
• Flexible Erase Capability
- Uniform 4 KByte sectors
- Four 8 KByte top and bottom parameter overlay
blocks
- One 32 KByte top and bottom overlay block
- Uniform 64 KByte overlay blocks
• Write-Suspend
- Suspend Program or Erase operation to access
another block/sector
• Software Reset (RST) mode
• Software Write Protection
- Individual-Block Write Protection with permanent
lock-down capability
- 64 KByte blocks, two 32 KByte blocks, and
eight 8 KByte parameter blocks
- Read Protection on top and bottom 8 KByte
parameter blocks
• Security ID
- One-Time Programmable (OTP) 2 KByte, Secure ID
- 64 bit unique, factory pre-programmed identifier
- User-programmable area
• Temperature Range
- Industrial: -40°C to +85°C
- Extended: -40°C to +105°C
• Packages Available
- 8-contact WDFN (6mm x 5mm)
- 8-lead SOIJ (5.28 mm)
- 24-ball TBGA (6mm x 8mm)
• All devices are RoHS compliant
Product Description
The Serial Quad I/O™ (SQI™) family of flash-memory
devices features a six-wire, 4-bit I/O interface that allows for
low-power, high-performance operation in a low pin-count
package. SST26VF032B/032BA also support full com-
mand-set compatibility to traditional Serial Peripheral Inter-
face (SPI) protocol. System designs using SQI flash devices
occupy less board space and ultimately lower system costs.
All members of the 26 Series, SQI family are manufactured
with proprietary, high-performance CMOS SuperFlash®
technology. The split-gate cell design and thick-oxide tun-
neling injector attain better reliability and manufacturability
compared with alternate approaches.
SST26VF032B/032BA significantly improve performance
and reliability, while lowering power consumption. These
devices write (Program or Erase) with a single power supply
of 2.3-3.6V. The total energy consumed is a function of the
applied voltage, current, and time of application. Since for
any given voltage range, the SuperFlash technology uses
less current to program and has a shorter erase time, the
total energy consumed during any Erase or Program opera-
tion is less than alternative flash memory technologies.
SST26VF032B/032BA are offered in 8-contact WDFN
(6 mm x 5 mm), 8-lead SOIJ (5.28 mm), and 24-ball
TBGA(6mm x 8mm). See
Figure 2-2
for pin assignments.
Two configurations are available upon order.
SST26VF032B default at power-up has the WP# and
HOLD# pins enabled, and the SIO2 and SIO3 pins dis-
abled,
to
initiate
SPI-protocol
operations.
SST26VF032BA default at power-up has the WP# and
HOLD# pins disabled, and the SIO2 and SIO3 pins
enabled, to initiate Quad I/O operations. See
“I/O Con-
figuration (IOC)” on page 12
for more information about
configuring WP#/HOLD# and SIO2/SIO3 pins.
2013-2016 Microchip Technology Inc.
DS20005218E-page 1
SST26VF032B / SST26VF032BA
TO OUR VALUED CUSTOMERS
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Most Current Data Sheet
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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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DS20005218E-page 2
2013-2016 Microchip Technology Inc.
SST26VF032B / SST26VF032BA
1.0
BLOCK DIAGRAM
FUNCTIONAL BLOCK DIAGRAM
FIGURE 1-1:
OTP
Address
Buffers
and
Latches
X - Decoder
SuperFlash
Memory
Y - Decoder
Control Logic
Page Buffer,
I/O Buffers
and
Data Latches
Serial Interface
WP# HOLD# SCK
CE#
SIO [3:0]
20005218 B1.0
2013-2016 Microchip Technology Inc.
DS20005218E-page 3
SST26VF032B / SST26VF032BA
2.0
PIN DESCRIPTION
PIN DESCRIPTION FOR
8-LEAD SOIJ
1
2
8
7
FIGURE 2-1:
FIGURE 2-2:
PIN DESCRIPTION FOR
8-CONTACT WDFN
1
8
CE#
SO/SIO1
WP#/SIO2
VSS
VDD
HOLD/SIO3
SCK
SI/SIO0
CE#
SO/SIO1
WP#/SIO2
V
SS
V
DD
HOLD/SIO3
SCK
SI/SIO0
2
7
Top View
3
4
6
5
3
Top
View
6
4
5
20005218 08-soic S2A P1.0
20005218 08-wson QA P1.0
FIGURE 2-3:
PIN DESCRIPTION FOR 24-BALL TBGA
4
NC
3
NC
2
NC
1
NC
NC
NC
NC
NC
NC
SCK
CE#
S0/
SIO1
NC
NC
V
SS
NC
SI/
SIO0
NC
NC
V
DD
WP#/ HOLD#/
SIO2 SIO3
NC
NC
A
B
C
D
E
F
20005218 T4D-P1.0
DS20005218E-page 4
2013-2016 Microchip Technology Inc.
SST26VF032B / SST26VF032BA
TABLE 2-1:
Symbol
SCK
PIN DESCRIPTION
Pin Name
Serial Clock
Functions
To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock
input, while output data is shifted out on the falling edge of the clock input.
To transfer commands, addresses, or data serially into the device or data out of
the device. Inputs are latched on the rising edge of the serial clock. Data is
shifted out on the falling edge of the serial clock. The Enable Quad I/O (EQIO)
command instruction configures these pins for Quad I/O mode.
To transfer commands, addresses or data serially into the device. Inputs are
latched on the rising edge of the serial clock. SI is the default state after a power
on reset.
To transfer data serially out of the device. Data is shifted out on the falling edge
of the serial clock. SO is the default state after a power on reset.
The device is enabled by a high to low transition on CE#. CE# must remain low
for the duration of any command sequence; or in the case of Write operations,
for the command/data input sequence.
The WP# is used in conjunction with the WPEN and IOC bits in the Configura-
tion register to prohibit write operations to the Block-Protection register. This pin
only works in SPI, single-bit and dual-bit Read mode.
Temporarily stops serial communication with the SPI Flash memory while the
device is selected. This pin only works in SPI, single-bit and dual-bit Read mode
and must be tied high when not in use.
To provide power supply voltage.
SIO[3:0]
Serial Data
Input/Output
SI
Serial Data Input
for SPI mode
Serial Data Output
for SPI mode
Chip Enable
SO
CE#
WP#
Write Protect
HOLD#
Hold
V
DD
V
SS
Power Supply
Ground
2013-2016 Microchip Technology Inc.
DS20005218E-page 5
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