Multi-Purpose Flash Plus + SRAM ComboMemory
SST32HF1622C
SST32HF16x2x / 32x2x / 6482x16/32/64Mb Flash + 4/8Mb SRAM, 32Mb Flash + 8Mb SRAM
(x16) MCP ComboMemories
EOL Data Sheet
FEATURES:
• ComboMemories organized as:
– SST32HF1622C: 1M x16 Flash + 128K x16 SRAM
• Single 2.7-3.3V Read and Write Operations
• Concurrent Operation
– Read from or Write to SRAM while
Erase/Program Flash
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption:
– Active Current: 15 mA (typical) for
Flash or SRAM Read
– Standby Current: 12 µA (typical)
• Flexible Erase Capability
– Uniform 2 KWord sectors
– Uniform 32 KWord size blocks
• Erase-Suspend/Erase-Resume Capabilities
• Security-ID Feature
– SST: 128 bits; User: 128 bits
• Hardware Block-Protection/WP# Input Pin
– Top Block-Protection (top 32 KWord)
• Fast Read Access Times:
– Flash: 70 ns
– SRAM: 70 ns
• Latched Address and Data for Flash
• Flash Fast Erase and Word-Program:
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 40 ms (typical)
– Word-Program Time: 7 µs (typical)
• Flash Automatic Erase and Program Timing
– Internal V
PP
Generation
• Flash End-of-Write Detection
– Toggle Bit
– Data# Polling
• CMOS I/O Compatibility
• JEDEC Standard Command Set
• Package Available
– 63-ball LFBGA (8mm x 10mm x 1.4mm)
– 62-ball LFBGA (8mm x 10mm x 1.4mm)
• All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST32HF1622C ComboMemory device integrates a
CMOS flash memory bank with a CMOS SRAM memory
bank in a Multi-Chip Package (MCP), manufactured with
SST’s proprietary, high performance SuperFlash technol-
ogy. The SST32HF1622C device uses standard SRAM.
Featuring high performance Word-Program, the flash
memory bank provides a maximum Word-Program time of
7 µsec. To protect against inadvertent flash write, the
SST32HF1622C device contains on-chip hardware and
software data protection schemes. The SST32HF1622C
device offers a guaranteed endurance of 10,000 cycles.
Data retention is rated at greater than 100 years.
The SST32HF1622C device consists of two independent
memory banks with respective bank enable signals. The
Flash and SRAM memory banks are superimposed in the
same memory address space. Both memory banks share
common address lines, data lines, WE# and OE#. The
memory bank selection is done by memory bank enable
signals. The SRAM bank enable signal, BES# selects the
SRAM bank. The flash memory bank enable signal, BEF#
©2008 Silicon Storage Technology, Inc.
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1
selects the flash memory bank. The WE# signal has to be
used with Software Data Protection (SDP) command
sequence when controlling the Erase and Program opera-
tions in the flash memory bank. The SDP command
sequence protects the data stored in the flash memory
bank from accidental alteration.
The SST32HF1622C provides the added functionality of
being able to simultaneously read from or write to the
SRAM bank while erasing or programming in the flash
memory bank. The SRAM memory bank can be read or
written while the flash memory bank performs Sector-
Erase, Bank-Erase, or Word-Program concurrently. All
flash memory Erase and Program operations will automati-
cally latch the input address and data signals and complete
the operation in background without further input stimulus
requirement. Once the internally controlled Erase or Pro-
gram cycle in the flash bank has commenced, the SRAM
bank can be accessed for Read or Write.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF+ and ComboMemory are trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
Multi-Purpose Flash Plus + SRAM ComboMemory
SST32HF1622C
EOL Data Sheet
The SST32HF1622C device is suited for applications that
use both flash memory and SRAM memory to store code
or data. For systems requiring low power and small form
factor, the SST32HF1622C device significantly improves
performance and reliability while lowering power consump-
tion when compared with multiple chip solutions. The
SST32HF1622C inherently uses less energy during Erase
and Program operations than alternative flash technolo-
gies. The total energy consumed is a function of the
applied voltage, current, and time of application. Since, for
any given voltage range, SuperFlash technology uses less
current to program and has a shorter erase time, the total
energy consumed during any Erase or Program operation
is less than alternative flash technologies.
SuperFlash technology provides fixed Erase and Program
times independent of the number of Erase/Program cycles
that have occurred. Therefore the system software or hard-
ware does not have to be modified or de-rated as is neces-
sary with alternative flash technologies, whose Erase and
Program times increase with accumulated Erase/Program
cycles.
Concurrent Read/Write Operation
The SST32HF1622C provides the unique benefit of being
able to read from or write to SRAM, while simultaneously
erasing or programming the flash. This allows data alter-
ation code to be executed from SRAM, while altering the
data in flash. See Figure 27 for a flowchart. The following
table lists all valid states.
Concurrent Read/Write State Table
Flash
Program/Erase
Program/Erase
SRAM
Read
Write
The device will ignore all SDP commands when an Erase
or Program operation is in progress. Note that Product
Identification commands use SDP; therefore, these com-
mands will also be ignored while an Erase or Program
operation is in progress.
Flash Read Operation
The Read operation of the SST32HF1622C device is con-
trolled by BEF# and OE#. Both have to be low, with WE#
high, for the system to obtain data from the outputs. BEF#
is used for flash memory bank selection. When BEF# is
high, the chip is deselected and only standby power is
consumed. OE# is the output control and is used to gate
data from the output pins. The data bus is in high imped-
ance state when OE# is high. Refer to Figure 7 for further
details.
Device Operation
The SST32HF1622C uses BES1#, BES2 and BEF# to
control operation of either the flash or the SRAM memory
bank. When BEF# is low, the flash bank is activated for
Read, Program or Erase operation. When BES1# is low,
and BES2 is high the SRAM is activated for Read and
Write operation. BEF# and BES1# cannot be at low level,
and BES2 cannot be at high level at the same time.
If all
bank enable signals are asserted, bus contention will
result and the device may suffer permanent damage.
All address, data, and control lines are shared by flash and
SRAM memory banks which minimizes power consump-
tion and loading. The device goes into standby when BEF#
and BES1# bank enables are raised to V
IHC
(Logic High) or
when BEF# is high and BES2 is low.
©2008 Silicon Storage Technology, Inc.
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Multi-Purpose Flash Plus + SRAM ComboMemory
SST32HF1622C
EOL Data Sheet
Flash Word-Program Operation
The flash memory bank of the SST32HF1622C device is
programmed on a word-by-word basis. Before Program
operations, the memory must be erased first. The Program
operation consists of three steps. The first step is the three-
byte load sequence for Software Data Protection. The sec-
ond step is to load word address and word data. During the
Word-Program operation, the addresses are latched on the
falling edge of either BEF# or WE#, whichever occurs last.
The data is latched on the rising edge of either BEF# or
WE#, whichever occurs last. The third step is the internal
Program operation which is initiated after the rising edge of
the fourth WE# or BEF#, whichever occurs first. The Pro-
gram operation, once initiated, will be completed, within 10
µs. See Figures 8 and 9 for WE# and BEF# controlled Pro-
gram operation timing diagrams and Figure 22 for flow-
charts. During the Program operation, the only valid flash
Read operations are Data# Polling and Toggle Bit. During
the internal Program operation, the host is free to perform
additional tasks. During the command sequence, WP#
should be statically held high or low. Any SDP commands
loaded during the internal Program operation will be
ignored.
Erase-Suspend/Erase-Resume Commands
The Erase-Suspend operation temporarily suspends a
Sector- or Block-Erase operation thus allowing data to be
read from any memory location, or program data into any
sector/block that is not suspended for an Erase operation.
The operation is executed by issuing one byte command
sequence with Erase-Suspend command (B0H). The
device automatically enters read mode typically within 20
µs after the Erase-Suspend command had been issued.
Valid data can be read from any sector or block that is not
suspended from an Erase operation. Reading at address
location within erase-suspended sectors/blocks will output
DQ
2
toggling and DQ
6
at “1”. While in Erase-Suspend
mode, a Word-Program operation is allowed except for the
sector or block selected for Erase-Suspend.
To resume Sector-Erase or Block-Erase operation which has
been suspended the system must issue Erase Resume
command. The operation is executed by issuing one byte
command sequence with Erase Resume command (30H)
at any address in the last Byte sequence.
Flash Chip-Erase Operation
The SST32HF1622C provides a Chip-Erase operation,
which allows the user to erase the entire memory array to
the “1” state. This is useful when the entire device must be
quickly erased.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command
(10H) at address 5555H in the last byte sequence. The
Erase operation begins with the rising edge of the sixth
WE# or BEF#, whichever occurs first. During the Erase
operation, the only valid read is Toggle Bit or Data# Polling.
See Table 6 for the command sequence, Figure 11 for tim-
ing diagram, and Figure 26 for the flowchart. Any com-
mands issued during the Chip-Erase operation are
ignored.
Flash Sector/Block-Erase Operation
The Flash Sector/Block-Erase operation allows the system
to erase the device on a sector-by-sector (or block-by-
block) basis. The SST32HF1622C offers both Sector-
Erase and Block-Erase mode. The sector architecture is
based on uniform sector size of 2 KWord. The Block-Erase
mode is based on uniform block size of 32 KWord. The
Sector-Erase operation is initiated by executing a six-byte
command sequence with Sector-Erase command (30H)
and sector address (SA) in the last bus cycle. The address
lines A
MS
-A
11
are used to determine the sector address.
The Block-Erase operation is initiated by executing a six-
byte command sequence with Block-Erase command
(50H) and block address (BA) in the last bus cycle. The
address lines A
MS
-A
15
are used to determine the block
address. The sector or block address is latched on the fall-
ing edge of the sixth WE# pulse, while the command (30H
or 50H) is latched on the rising edge of the sixth WE#
pulse. The internal Erase operation begins after the sixth
WE# pulse. The End-of-Erase operation can be deter-
mined using either Data# Polling or Toggle Bit methods.
See Figures 13 and 14 for timing waveforms. Any com-
mands issued during the Sector- or Block-Erase operation
are ignored, WP# should be statically held high or low.
Write Operation Status Detection
The SST32HF1622C provides two software means to
detect the completion of a write (Program or Erase) cycle,
in order to optimize the system Write cycle time. The soft-
ware detection includes two status bits: Data# Polling
(DQ
7
) and Toggle Bit (DQ
6
). The End-of-Write detection
mode is enabled after the rising edge of WE#, which ini-
tiates the internal Program or Erase operation.
©2008 Silicon Storage Technology, Inc.
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Multi-Purpose Flash Plus + SRAM ComboMemory
SST32HF1622C
EOL Data Sheet
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the Write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to con-
flict with either DQ
7
or DQ
6.
In order to prevent spurious
rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If both reads are valid, then the
device has completed the Write cycle, otherwise the rejec-
tion is valid.
TABLE 1: Write Operation Status
Status
Normal
Standard
Operation Program
Standard
Erase
Erase-
Suspend
Mode
Read from
Erase-Suspended
Sector/Block
Read from
Non- Erase-Suspended
Sector/Block
Program
DQ
7
DQ
7
#
0
1
DQ
6
Toggle
Toggle
1
DQ
2
No Toggle
Toggle
Toggle
Data
Data
Data
DQ
7
#
Toggle
N/A
T1.0 1253
Flash Data# Polling (DQ
7
)
When the SST32HF1622C flash memory banks are in the
internal Program operation, any attempt to read DQ
7
will
produce the complement of the true data. Once the Pro-
gram operation is completed, DQ
7
will produce true data.
Note that even though DQ
7
may have valid data immedi-
ately following the completion of an internal Write opera-
tion, the remaining data outputs may still be invalid: valid
data on the entire data bus will appear in subsequent suc-
cessive Read cycles after an interval of 1 µs. During inter-
nal Erase operation, any attempt to read DQ
7
will produce
a ‘0’. Once the internal Erase operation is completed, DQ
7
will produce a ‘1’. The Data# Polling is valid after the rising
edge of the fourth WE# (or BEF#) pulse for Program opera-
tion. For Sector- or Block-Erase, the Data# Polling is valid
after the rising edge of the sixth WE# (or BEF#) pulse. See
Figure 10 for Data# Polling timing diagram and Figure 23
for a flowchart.
Note:
DQ
7
and DQ
2
require a valid address when reading
status information.
Flash Memory Data Protection
The SST32HF1622C flash memory bank provides both
hardware and software features to protect nonvolatile data
from inadvertent writes.
Flash Hardware Data Protection
Noise/Glitch Protection: A WE# or BEF# pulse of less than
5 ns will not initiate a Write cycle.
V
DD
Power Up/Down Detection: The Write operation is
inhibited when V
DD
is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, BEF# high, or WE#
high will inhibit the flash Write operation. This prevents
inadvertent writes during power-up or power-down.
Toggle Bits (DQ6 and DQ2)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
6
will produce alternating “1”s
and “0”s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ
6
bit will
stop toggling. The device is then ready for the next opera-
tion. For Sector-, Block-, or Chip-Erase, the toggle bit (DQ
6
)
is valid after the rising edge of sixth WE# (or BEF#) pulse.
DQ
6
will be set to “1” if a Read operation is attempted on an
Erase-Suspended Sector/Block. If Program operation is ini-
tiated in a sector/block not selected in Erase-Suspend
mode, DQ
6
will toggle.
An additional Toggle Bit is available on DQ
2
, which can be
used in conjunction with DQ
6
to check whether a particular
sector is being actively erased or erase-suspended. Table 1
shows detailed status bits information. The Toggle Bit
(DQ
2
) is valid after the rising edge of the last WE# (or
BEF#) pulse of Write operation. See Figure 11 for Toggle
Bit timing diagram and Figure 23 for a flowchart.
©2008 Silicon Storage Technology, Inc.
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Multi-Purpose Flash Plus + SRAM ComboMemory
SST32HF1622C
EOL Data Sheet
Hardware Block Protection
The SST32HF1622C supports top hardware block pro-
tection, which protects the top 32 KWord block of the
device. The Boot Block address ranges are described in
Table 2. Program and Erase operations are prevented on
the 32 KWord when WP# is low. If WP# is left floating, it
is internally held high via a pull-up resistor, and the Boot
Block is unprotected, enabling Program and Erase oper-
ations on that block.
TABLE 2: Boot Block Address Ranges
Product
Top Boot Block
SST32HF1622C
0F8000H-0FFFFFH
T2.1 1253
SRAM Read
The SRAM Read operation of the SST32HF1622C is con-
trolled by OE# and BES1#, both have to be low with WE#
and BES2 high for the system to obtain data from the out-
puts. BES1# and BES2 are used for SRAM bank selection.
OE# is the output control and is used to gate data from the
output pins. The data bus is in high impedance state when
OE# is high. Refer to the Read cycle timing diagram, Fig-
ure 4, for further details.
SRAM Write
The SRAM Write operation of the SST32HF1622C is con-
trolled by WE# and BES1#, both have to be low, BES2
must be high for the system to write to the SRAM. During
the Word-Write operation, the addresses and data are ref-
erenced to the rising edge of either BES1#, WE#, or the
falling edge of BES2 whichever occurs first. The write time
is measured from the last falling edge of BES#1 or WE# or
the rising edge of BES2 to the first rising edge of BES1#, or
WE# or the falling edge of BES2. Refer to the Write cycle
timing diagrams, Figures 5 and 6, for further details.
Address Range
Hardware Reset (RST#)
The RST# pin provides a hardware method of resetting the
device to read array data. When the RST# pin is held low
for at least T
RP,
any in-progress operation will terminate and
return to Read mode. When no internal Program/Erase
operation is in progress, a minimum period of T
RHR
is
required after RST# is driven high before a valid Read can
take place (see Figure 18).
The Erase or Program operation that has been interrupted
needs to be reinitiated after the device resumes normal
operation mode to ensure data integrity.
Product Identification
The Product Identification mode identifies the devices as
the SST32HF1622C and manufacturer as SST.
This
mode may be accessed by software operations only.
The hardware device ID Read operation, which is typi-
cally used by programmers, cannot be used on this
device because of the shared lines between flash and
SRAM in the multi-chip package. Therefore, applica-
tion of high voltage to pin A
9
may damage this device.
Users may use the software Product Identification opera-
tion to identify the part (i.e., using the device ID) when using
multiple manufacturers in the same socket. For details, see
Tables 5 and 6 for software operation, Figure 15 for the
software ID entry and read timing diagram and Figure 24
for the ID entry command sequence flowchart.
TABLE 3: Product Identification
Address
Manufacturer’s ID
Device ID
SST32HF1622C
0001H
234AH
T3.2 1253
Flash Software Data Protection (SDP)
The SST32HF1622C provides the JEDEC approved soft-
ware data protection scheme for all flash memory bank
data alteration operations, i.e., Program and Erase. Any
Program operation requires the inclusion of a series of
three-byte sequence. The three byte-load sequence is
used to initiate the Program operation, providing optimal
protection from inadvertent Write operations, e.g., during
the system power-up or power-down. Any Erase operation
requires the inclusion of six-byte load sequence. The
SST32HF1622C device is shipped with the software data
protection permanently enabled. See Table 6 for the spe-
cific software command codes. During SDP command
sequence, invalid commands will abort the device to Read
mode, within T
RC.
The contents of DQ
15
-DQ
8
can be V
IL
or
V
IH,
but no other value, during any SDP command
sequence.
Data
BFH
0000H
©2008 Silicon Storage Technology, Inc.
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Microchip MCU
