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Multi-Purpose Flash Plus + PSRAM ComboMemory

SST32HF32A2

SST32HF32A32Mb Flash + 16Mb SRAM

(x16) MCP ComboMemories

Preliminary Specifications

FEATURES:

• ComboMemories organized as:

– 2M x16 Flash + 1024K x16 PSRAM

• Single 2.7-3.3V Read and Write Operations

• Concurrent Operation

– Read from or Write to PSRAM while

Erase/Program Flash

• Superior Reliability

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

• Low Power Consumption:

– Active Current: 15 mA (typical) for

Flash or PSRAM Read

– Standby Current: 60 µA (typical)

• Flexible Erase Capability

– Uniform 2 KWord sectors

– Uniform 32 KWord size blocks

• Erase-Suspend/Erase-Resume Capabilities

• Security-ID Feature

– SST: 128 bits; User: 128 bits

• Hardware Block-Protection/WP# Input Pin

– Top Block-Protection (top 32 KWord)

for SST32HF32A2

• Fast Read Access Times:

– Flash: 70 ns

– PSRAM: 70 ns

• Latched Address and Data for Flash

• Flash Fast Erase and Word-Program:

– Sector-Erase Time: 18 ms (typical)

– Block-Erase Time: 18 ms (typical)

– Chip-Erase Time: 40 ms (typical)

– Word-Program Time: 7 µs (typical)

• Flash Automatic Erase and Program Timing

– Internal V

Generation

• Flash End-of-Write Detection

– Toggle Bit

– Data# Polling

• CMOS I/O Compatibility

• JEDEC Standard Command Set

• Package Available

– 63-ball LFBGA (8mm x 10mm x 1.4mm)

– 62-ball LFBGA (8mm x 10mm x 1.4mm)

• All non-Pb (lead-free) devices are RoHS compliant

PRODUCT DESCRIPTION

The SST32HF32A2 ComboMemory devices integrate a

CMOS flash memory bank with a CMOS PseudoSRAM

(PSRAM) memory bank in a Multi-Chip Package (MCP),

manufactured with SST’s proprietary, high-performance

SuperFlash technology.

Featuring high-performance Word-Program, the flash

memory bank provides a maximum Word-Program time of

7 µsec. To protect against inadvertent flash write, the

SST32HF32A2 devices contain on-chip hardware and soft-

ware data protection schemes. The SST32HF32A2

devices offer a guaranteed endurance of 10,000 cycles.

Data retention is rated at greater than 100 years.

The SST32HF32A2 devices consist of two independent

memory banks with respective bank enable signals. The

flash and PSRAM memory banks are superimposed in the

same memory address space. Both memory banks share

common address lines, data lines, WE# and OE#. The

memory bank selection is done by memory bank enable

signals. The PSRAM bank enable signal, BES# selects the

PSRAM bank. The flash memory bank enable signal,

S71261-01-000

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BEF# selects the flash memory bank. The WE# signal has

to be used with Software Data Protection (SDP) command

sequence when controlling the Erase and Program opera-

tions in the flash memory bank. The SDP command

sequence protects the data stored in the flash memory

bank from accidental alteration.

The SST32HF32A2 provide the added functionality of

being able to simultaneously read from or write to the

PSRAM bank while erasing or programming in the flash

memory bank. The PSRAM memory bank can be read or

written while the flash memory bank performs Sector-

Erase, Bank-Erase, or Word-Program concurrently. All

flash memory Erase and Program operations will automati-

cally latch the input address and data signals and complete

the operation in background without further input stimulus

requirement. Once the internally controlled Erase or Pro-

gram cycle in the flash bank has commenced, the PSRAM

bank can be accessed for Read or Write.

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

MPF+ and ComboMemory are trademarks of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

Multi-Purpose Flash Plus + PSRAM ComboMemory

SST32HF32A2

Preliminary Specifications

The SST32HF32A2 devices are suited for applications that

use both flash memory and PSRAM memory to store code

or data. For systems requiring low power and small form

factor, the SST32HF32A2 devices significantly improve

performance and reliability, while lowering power consump-

tion, when compared with multiple chip solutions. The

SST32HF32A2 inherently use less energy during erase

and program than alternative flash technologies. The total

energy consumed is a function of the applied voltage, cur-

rent, and time of application. Since for any given voltage

range, the SuperFlash technology uses less current to pro-

gram and has a shorter erase time, the total energy con-

sumed during any Erase or Program operation is less than

alternative flash technologies.

The SuperFlash technology provides fixed Erase and Pro-

gram times, independent of the number of Erase/Program

cycles that have occurred. Therefore the system software

or hardware does not have to be modified or de-rated as is

necessary with alternative flash technologies, whose Erase

and Program times increase with accumulated Erase/Pro-

gram cycles.

Concurrent Read/Write Operation

The SST32HF32A2 provide the unique benefit of being

able to read from or write to PSRAM, while simultaneously

erasing or programming the flash. This allows data alter-

ation code to be executed from PSRAM, while altering the

data in flash. See Figure 26 for a flowchart. The following

table lists all valid states.

ONCURRENT

EAD

RITE

TATE

ABLE

Flash

Program/Erase

PSRAM

Read

Write

The device will ignore all SDP commands when an Erase

or Program operation is in progress. Note that Product

Identification commands use SDP; therefore, these com-

mands will also be ignored while an Erase or Program

operation is in progress.

Flash Read Operation

The Read operation of the SST32HF32A2 devices is con-

trolled by BEF# and OE#. Both have to be low, with WE#

high, for the system to obtain data from the outputs. BEF#

is used for flash memory bank selection. When BEF# is

high, the chip is deselected and only standby power is

consumed. OE# is the output control and is used to gate

data from the output pins. The data bus is in high imped-

ance state when OE# is high. Refer to Figure 6 for further

details.

Device Operation

The SST32HF32A2 use BES1#, BES2 and BEF# to con-

trol operation of either the flash or the PSRAM memory

bank. When BEF# is low, the flash bank is activated for

Read, Program or Erase operation. When BES1# is low,

and BES2 is high the PSRAM is activated for Read and

Write operation. BEF# and BES1# cannot be at low level,

and BES2 cannot be at high level at the same time.

If all

bank enable signals are asserted, bus contention will

result and the device may suffer permanent damage.

All address, data, and control lines are shared by flash and

PSRAM memory banks which minimizes power consump-

tion and loading. The device goes into standby when BEF#

and BES1# bank enables are raised to V

IHC

(Logic High) or

when BEF# is high and BES2 is low.

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Multi-Purpose Flash Plus + PSRAM ComboMemory

SST32HF32A2

Preliminary Specifications

Flash Word-Program Operation

The flash memory bank of the SST32HF32A2 devices is

programmed on a word-by-word basis. Before Program

operations, the memory must be erased first. The Program

operation consists of three steps. The first step is the three-

byte load sequence for Software Data Protection. The sec-

ond step is to load word address and word data. During the

Word-Program operation, the addresses are latched on the

falling edge of either BEF# or WE#, whichever occurs last.

The data is latched on the rising edge of either BEF# or

WE#, whichever occurs last. The third step is the internal

Program operation which is initiated after the rising edge of

the fourth WE# or BEF#, whichever occurs first. The Pro-

gram operation, once initiated, will be completed, within 10

µs. See Figures 7 and 8 for WE# and BEF# controlled Pro-

gram operation timing diagrams and Figure 21 for flow-

charts. During the Program operation, the only valid flash

Read operations are Data# Polling and Toggle Bit. During

the internal Program operation, the host is free to perform

additional tasks. During the command sequence, WP#

should be statically held high or low. Any SDP commands

loaded during the internal Program operation will be

ignored.

Erase-Suspend/Erase-Resume Commands

The Erase-Suspend operation temporarily suspends a

Sector- or Block-Erase operation thus allowing data to be

read from any memory location, or program data into any

sector/block that is not suspended for an Erase operation.

The operation is executed by issuing one byte command

sequence with Erase-Suspend command (B0H). The

device automatically enters read mode typically within 20

µs after the Erase-Suspend command had been issued.

Valid data can be read from any sector or block that is not

suspended from an Erase operation. Reading at address

location within erase-suspended sectors/blocks will output

toggling and DQ

at “1”. While in Erase-Suspend

mode, a Word-Program operation is allowed except for the

sector or block selected for Erase-Suspend.

To resume Sector-Erase or Block-Erase operation which has

been suspended the system must issue Erase Resume

command. The operation is executed by issuing one byte

command sequence with Erase Resume command (30H)

at any address in the last Byte sequence.

Flash Chip-Erase Operation

The SST32HF32A2 provide a Chip-Erase operation,

which allows the user to erase the entire memory array to

the “1” state. This is useful when the entire device must be

quickly erased.

The Chip-Erase operation is initiated by executing a six-

byte command sequence with Chip-Erase command

(10H) at address 5555H in the last byte sequence. The

Erase operation begins with the rising edge of the sixth

WE# or BEF#, whichever occurs first. During the Erase

operation, the only valid read is Toggle Bit or Data# Polling.

See Table 5 for the command sequence, Figure 10 for tim-

ing diagram, and Figure 25 for the flowchart. Any com-

mands issued during the Chip-Erase operation are

ignored.

Flash Sector/Block-Erase Operation

The Flash Sector/Block-Erase operation allows the system

to erase the device on a sector-by-sector (or block-by-

block) basis. The SST32HF32A2 offer both Sector-Erase

and Block-Erase mode. The sector architecture is based

on uniform sector size of 2 KWord. The Block-Erase mode

is based on uniform block size of 32 KWord. The Sector-

Erase operation is initiated by executing a six-byte com-

mand sequence with Sector-Erase command (30H) and

sector address (SA) in the last bus cycle. The address lines

-A

are used to determine the sector address. The

Block-Erase operation is initiated by executing a six-byte

command sequence with Block-Erase command (50H)

and block address (BA) in the last bus cycle. The address

lines A

-A

are used to determine the block address.

The sector or block address is latched on the falling edge of

the sixth WE# pulse, while the command (30H or 50H) is

latched on the rising edge of the sixth WE# pulse. The

internal Erase operation begins after the sixth WE# pulse.

The End-of-Erase operation can be determined using

either Data# Polling or Toggle Bit methods. See Figures 12

and 13 for timing waveforms. Any commands issued during

the Sector- or Block-Erase operation are ignored, WP#

should be statically held high or low.

Write Operation Status Detection

The SST32HF32A2 provide two software means to detect

the completion of a write (Program or Erase) cycle, in order

to optimize the system Write cycle time. The software

detection includes two status bits: Data# Polling (DQ

) and

Toggle Bit (DQ

). The End-of-Write detection mode is

enabled after the rising edge of WE#, which initiates the

internal Program or Erase operation.

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Multi-Purpose Flash Plus + PSRAM ComboMemory

SST32HF32A2

Preliminary Specifications

The actual completion of the nonvolatile write is asynchro-

nous with the system; therefore, either a Data# Polling or

Toggle Bit read may be simultaneous with the completion

of the Write cycle. If this occurs, the system may possibly

get an erroneous result, i.e., valid data may appear to con-

flict with either DQ

or DQ

In order to prevent spurious

rejection, if an erroneous result occurs, the software routine

should include a loop to read the accessed location an

additional two (2) times. If both reads are valid, then the

device has completed the Write cycle, otherwise the rejec-

tion is valid.

TABLE 1: W

RITE

PERATION

TATUS

Status

Normal

Standard

Operation Program

Standard

Erase

Erase-

Suspend

Mode

Read from

Erase-Suspended

Sector/Block

Read from

Non- Erase-Suspended

Sector/Block

Program

Toggle

No Toggle

Toggle

Data

Toggle

N/A

T1.0 1261

Flash Data# Polling (DQ

)

When the SST32HF32A2 flash memory banks are in the

internal Program operation, any attempt to read DQ

will

produce the complement of the true data. Once the Pro-

gram operation is completed, DQ

will produce true data.

Note that even though DQ

may have valid data immedi-

ately following the completion of an internal Write opera-

tion, the remaining data outputs may still be invalid: valid

data on the entire data bus will appear in subsequent suc-

cessive Read cycles after an interval of 1 µs. During inter-

nal Erase operation, any attempt to read DQ

will produce

a ‘0’. Once the internal Erase operation is completed, DQ

will produce a ‘1’. The Data# Polling is valid after the rising

edge of the fourth WE# (or BEF#) pulse for Program opera-

tion. For Sector- or Block-Erase, the Data# Polling is valid

after the rising edge of the sixth WE# (or BEF#) pulse. See

Figure 9 for Data# Polling timing diagram and Figure 22 for

a flowchart.

Note:

and DQ

require a valid address when reading

status information.

Flash Memory Data Protection

The SST32HF32A2 flash memory bank provides both

hardware and software features to protect nonvolatile data

from inadvertent writes.

Flash Hardware Data Protection

Noise/Glitch Protection: A WE# or BEF# pulse of less than

5 ns will not initiate a Write cycle.

Power Up/Down Detection: The Write operation is

inhibited when V

is less than 1.5V.

Write Inhibit Mode: Forcing OE# low, BEF# high, or WE#

high will inhibit the flash Write operation. This prevents

inadvertent writes during power-up or power-down.

Toggle Bits (DQ6 and DQ2)

During the internal Program or Erase operation, any con-

secutive attempts to read DQ

will produce alternating “1”s

and “0”s, i.e., toggling between 1 and 0. When the internal

Program or Erase operation is completed, the DQ

bit will

stop toggling. The device is then ready for the next opera-

tion. For Sector-, Block-, or Chip-Erase, the toggle bit (DQ

)

is valid after the rising edge of sixth WE# (or BEF#) pulse.

will be set to “1” if a Read operation is attempted on an

Erase-Suspended Sector/Block. If Program operation is ini-

tiated in a sector/block not selected in Erase-Suspend

mode, DQ

will toggle.

An additional Toggle Bit is available on DQ

, which can be

used in conjunction with DQ

to check whether a particular

sector is being actively erased or erase-suspended. Table 1

shows detailed status bits information. The Toggle Bit

(DQ

) is valid after the rising edge of the last WE# (or

BEF#) pulse of Write operation. See Figure 10 for Toggle

Bit timing diagram and Figure 22 for a flowchart.

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Multi-Purpose Flash Plus + PSRAM ComboMemory

SST32HF32A2

Preliminary Specifications

Hardware Block Protection

The SST32HF32A2 support top hardware block protection,

which protects the top 32 KWord block of the device. The

Boot Block address is 1F8000H-1FFFFFH. Program and

Erase operations are prevented on the 32 KWord when

WP# is low. If WP# is left floating, it is internally held high

via a pull-up resistor, and the Boot Block is unprotected,

enabling Program and Erase operations on that block.

PSRAM Read

The PSRAM Read operation of the SST32HF32A2 is con-

trolled by OE# and BES1#, both have to be low with WE#

and BES2 high for the system to obtain data from the out-

puts. BES1# and BES2 are used for PSRAM bank selec-

tion. OE# is the output control and is used to gate data from

the output pins. The data bus is in high impedance state

when OE# is high. Refer to the Read cycle timing diagram,

Figure 3, for further details.

Hardware Reset (RST#)

The RST# pin provides a hardware method of resetting the

device to read array data. When the RST# pin is held low

for at least T

RP,

any in-progress operation will terminate and

return to Read mode. When no internal Program/Erase

operation is in progress, a minimum period of T

RHR

required after RST# is driven high before a valid Read can

take place (see Figure 17).

The Erase or Program operation that has been interrupted

needs to be reinitiated after the device resumes normal

operation mode to ensure data integrity.

PSRAM Write

The PSRAM Write operation of the SST32HF32A2 is con-

trolled by WE# and BES1#, both have to be low, BES2

must be high for the system to write to the PSRAM. During

the Word-Write operation, the addresses and data are ref-

erenced to the rising edge of either BES1#, WE#, or the

falling edge of BES2 whichever occurs first. The write time

is measured from the last falling edge of BES#1 or WE# or

the rising edge of BES2 to the first rising edge of BES1#, or

WE# or the falling edge of BES2. Refer to the Write cycle

timing diagrams, Figures 4 and 5, for further details.

Flash Software Data Protection (SDP)

The SST32HF32A2 provide the JEDEC approved software

data protection scheme for all flash memory bank data

alteration operations, i.e., Program and Erase. Any Pro-

gram operation requires the inclusion of a series of three-

byte sequence. The three byte-load sequence is used to

initiate the Program operation, providing optimal protection

from inadvertent Write operations, e.g., during the system

power-up or power-down. Any Erase operation requires the

inclusion of six-byte load sequence. The SST32HF32A2

devices are shipped with the software data protection per-

manently enabled. See Table 5 for the specific software

command codes. During SDP command sequence, invalid

commands will abort the device to Read mode, within T

RC.

The contents of DQ

-DQ

can be V

or V

IH,

but no other

value, during any SDP command sequence.

Product Identification

The Product Identification mode identifies the devices as

the SST32HF32A2 and manufacturer as SST.

This mode

may be accessed by software operations only. The

hardware device ID Read operation, which is typically

used by programmers, cannot be used on this device

because of the shared lines between flash and PSRAM

in the multi-chip package. Therefore, application of

high voltage to pin A

may damage this device.

Users

may use the software Product Identification operation to

identify the part (i.e., using the device ID) when using multi-

ple manufacturers in the same socket. For details, see

Tables 4 and 5 for software operation, Figure 14 for the

software ID entry and read timing diagram and Figure 23

for the ID entry command sequence flowchart.

TABLE 2: P

RODUCT

DENTIFICATION

Address

Manufacturer’s ID

Device ID

SST32HF32A2

0001H

235AH

T2.1 1261

Data

BFH

0000H

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