4 Megabit (256K x 16-Bit) Multi-Purpose Flash
SST39VF400
Advance Information
FEATURES:
• Organized as 256 K X 16
• Single 2.7-3.6V Read and Write Operations
• Superior Reliability
- Endurance: 100,000 Cycles (typical)
- Greater than 100 years Data Retention
• Low Power Consumption:
- Active Current: 15 mA (typical)
- Standby Current: 10 µA (typical)
- Auto Low Power Mode: 10 µA (typical)
• Small Sector-Erase Capability (128 sectors)
- Uniform 2 KWord sectors
• Block-Erase Capability (8 blocks)
- Uniform 32 KWord blocks
• Fast Read Access Time:
- 70 and 90 ns
• Latched Address and Data
• Fast Erase and Word-Program:
- Sector-Erase Time: 18 ms (typical)
- Block-Erase Time: 18 ms (typical)
- Chip-Erase Time: 70 ms (typical)
- Word-Program Time: 14 µs (typical)
- Chip Rewrite Time: 4 seconds (typical)
• Automatic Write Timing
- Internal V
PP
Generation
• End of Write Detection
- Toggle Bit
- Data# Polling
• CMOS I/O Compatibility
• JEDEC Standard
- Flash EEPROM Pinouts and command sets
• Packages Available
- 48-Pin TSOP (12mm x 20mm)
- 48-Ball TFBGA
1
2
3
4
5
6
7
PRODUCT DESCRIPTION
The SST39VF400 device is a 256K x 16 CMOS Multi-
Purpose Flash (MPF) manufactured with SST’s propri-
etary, high performance CMOS SuperFlash technology.
The split-gate cell design and thick oxide tunneling
injector attain better reliability and manufacturability
compared with alternate approaches. The SST39VF400
writes (Programs or Erases) with a 2.7-3.6V power
supply. The SST39VF400 conforms to JEDEC standard
pinouts for x16 memories.
Featuring high performance Word-Program, the
SST39VF400 device provides a typical Word-Program
time of 14 µsec. The entire memory can typically be
erased and programmed word-by-word in 4 seconds,
when using interface features such as Toggle Bit or
Data# Polling to indicate the completion of the Program
operation. To protect against inadvertent write, the
SST39VF400 has on-chip hardware and software data
protection schemes. Designed, manufactured, and
tested for a wide spectrum of applications, the
SST39VF400 is offered with a guaranteed endurance of
10,000 cycles. Data retention is rated at greater than 100
years.
The SST39VF400 device is suited for applications that
require convenient and economical updating of program,
configuration, or data memory. For all system applica-
tions, the SST39VF400 significantly improves perfor-
mance and reliability, while lowering power consump-
tion. The SST39VF400 inherently uses less energy
during Erase and Program than alternative flash tech-
nologies. When programming a flash device, the total
energy consumed is a function of the applied voltage,
current, and time of application. Since for any given
voltage range, the SuperFlash technology uses less
current to program and has a shorter erase time, the total
energy consumed during any Erase or Program opera-
tion is less than alternative flash technologies. The
SST39VF400 also improves flexibility while lowering the
cost for program, data, and configuration storage appli-
cations.
The SuperFlash technology provides fixed Erase and
Program times, independent of the number of Erase/
Program cycles that have occurred. Therefore the sys-
tem software or hardware does not have to be modified
or de-rated as is necessary with alternative flash tech-
nologies, whose Erase and Program times increase with
accumulated Erase/Program cycles.
To meet high density, surface mount requirements, the
SST39VF400 is offered in 48-pin TSOP and 48-ball
TFBGA packages. See Figures 1 and 2 for pinouts.
Device Operation
Commands are used to initiate the memory operation
functions of the device. Commands are written to the
device using standard microprocessor write sequences.
A command is written by asserting WE# low while
keeping CE# low. The address bus is latched on the
falling edge of WE# or CE#, whichever occurs last. The
data bus is latched on the rising edge of WE# or CE#,
whichever occurs first.
8
9
10
11
12
13
14
15
16
© 1999 Silicon Storage Technology, Inc.The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon Storage Technology, Inc.
342-06 7/99
These specifications are subject to change without notice.
1
4 Megabit Multi-Purpose Flash
SST39VF400
Advance Information
The SST39VF400 also has the
Auto Low Power
mode
which puts the device in a near standby mode after data
has been accessed with a valid Read operation. This
reduces the I
DD
active read current from typically 15 mA to
typically 200 µA. The Auto Low Power mode reduces the
typical I
DD
active read current to the range of 1 mA/MHz of
read cycle time. The device exits the Auto Low Power
mode with any address transition or control signal transi-
tion used to initiate another read cycle, with no access time
penalty.
Read
The Read operation of the SST39VF400 is controlled by
CE# and OE#, both have to be low for the system to obtain
data from the outputs. CE# is used for device selection.
When CE# is high, the chip is deselected and only standby
power is consumed. OE# is the output control and is used
to gate data from the output pins. The data bus is in high
impedance state when either CE# or OE# is high. Refer to
the Read cycle timing diagram for further details (Figure 3).
Word-Program Operation
The SST39VF400 is programmed on a word-by-word
basis. The Program operation consists of three steps. The
first step is the three-byte load sequence for Software Data
Protection. The second step is to load word address and
word data. During the Word-Program operation, the ad-
dresses are latched on the falling edge of either CE# or
WE#, whichever occurs last. The data is latched on the
rising edge of either CE# or WE#, whichever occurs first.
The third step is the internal Program operation which is
initiated after the rising edge of the fourth WE# or CE#,
whichever occurs first. The Program operation, once initi-
ated, will be completed within 20 µs. See Figures 4 and 5
for WE# and CE# controlled Program operation timing
diagrams and Figure 16 for flowcharts. During the Pro-
gram operation, the only valid reads are Data# Polling and
Toggle Bit. During the internal Program operation, the host
is free to perform additional tasks. Any commands issued
during the internal Program operation are ignored.
Sector/Block-Erase Operation
The Sector/Block-Erase operation allows the system to
erase the device on a sector-by-sector (or block-by-block)
basis. The SST39VF400 offers both small Sector-Erase
and Block-Erase mode. The sector architecture is based
on uniform sector size of 2 KWord. The Block-Erase mode
is based on uniform block size of 32 KWord. The Sector-
Erase operation is initiated by executing a six-byte com-
mand sequence with Sector-Erase command (30H) and
sector address (SA) in the last bus cycle. The address lines
A11-A17 are used to determine the sector address. The
Block-Erase operation is initiated by executing a six-byte
command sequence with Block-Erase command (50H)
© 1999 Silicon Storage Technology, Inc.
and block address (BA) in the last bus cycle. The address
lines A15-A17 are used to determine the block address.
The sector or block address is latched on the falling edge
of the sixth WE# pulse, while the command (30H or 50H)
is latched on the rising edge of the sixth WE# pulse. The
internal Erase operation begins after the sixth WE# pulse.
The end of Erase operation can be determined using either
Data# Polling or Toggle Bit methods. See Figures 9 and 10
for timing waveforms. Any commands issued during the
Sector or Block-Erase operation are ignored.
Chip-Erase Operation
The SST39VF400 provides a Chip-Erase operation, which
allows the user to erase the entire memory array to the “1”
state. This is useful when the entire device must be quickly
erased.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command
(10H) at address 5555H in the last byte sequence. The
Erase operation begins with the rising edge of the sixth
WE# or CE#, whichever occurs first. During the Erase
operation, the only valid read is Toggle Bit or Data# Polling.
See Table 4 for the command sequence, Figure 8 for timing
diagram, and Figure 19 for the flowchart. Any commands
issued during the Chip-Erase operation are ignored.
Write Operation Status Detection
The SST39VF400 provides two software means to detect
the completion of a Write (Program or Erase) cycle, in order
to optimize the system write cycle time. The software
detection includes two status bits: Data# Polling (DQ
7
) and
Toggle Bit (DQ
6
). The end of write detection mode is
enabled after the rising edge of WE#, which initiates the
internal Program or Erase operation.
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to
conflict with either DQ
7
or DQ
6
. In order to prevent spurious
rejection, if an erroneous result occurs, the software rou-
tine should include a loop to read the accessed location an
additional two (2) times. If both reads are valid, then the
device has completed the write cycle, otherwise the rejec-
tion is valid.
Data# Polling (DQ
7
)
When the SST39VF400 is in the internal Program opera-
tion, any attempt to read DQ
7
will produce the complement
of the true data. Once the Program operation is completed,
DQ
7
will produce true data. The device is then ready for the
next operation. During internal Erase operation, any at-
tempt to read DQ7 will produce a ‘0’. Once the internal
2
342-06 7/99
4 Megabit Multi-Purpose Flash
SST39VF400
Advance Information
Erase operation is completed, DQ7 will produce a ‘1’. The
Data# Polling is valid after the rising edge of fourth WE# (or
CE#) pulse for Program operation. For Sector, Block or
Chip-Erase, the Data# Polling is valid after the rising edge
of sixth WE# (or CE#) pulse. See Figure 6 for Data# Polling
timing diagram and Figure 17 for a flowchart.
Toggle Bit (DQ
6
)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
6
will produce alternating 1’s
and 0’s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ6 bit will
stop toggling. The device is then ready for the next opera-
tion. The Toggle Bit is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector,
Block or Chip-Erase, the Toggle Bit is valid after the rising
edge of sixth WE# (or CE#) pulse. See Figure 7 for Toggle
Bit timing diagram and Figure 17 for a flowchart.
Data Protection
The SST39VF400 provides both hardware and software
features to protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than
5 ns will not initiate a write cycle.
V
DD
Power Up/Down Detection: The Write operation is
inhibited when V
DD
is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Software Data Protection (SDP)
The SST39VF400 provides the JEDEC approved Soft-
ware Data Protection scheme for all data alteration opera-
tions, i.e., Program and Erase. Any Program operation
requires the inclusion of the three-byte sequence. The
three-byte load sequence is used to initiate the Program
operation, providing optimal protection from inadvertent
Write operations, e.g., during the system power-up or
power-down. Any Erase operation requires the inclusion of
six-byte sequence. The SST39VF400 device is shipped
with the Software Data Protection permanently enabled.
See Table 4 for the specific software command codes.
During SDP command sequence, invalid commands will
abort the device to Read mode within T
RC
. The contents of
DQ
15
-DQ
8
are “Don’t Care” during any SDP command
sequence.
Common Flash Memory Interface (CFI)
The SST39VF400 also contains the CFI information to
describe the characteristics of the device. In order to enter
the CFI Query mode, the system must write three-byte
sequence, same as Software ID Entry command with 98H
(CFI Query command) to address 5555H in the last byte
sequence. Once the device enters the CFI Query mode, the
system can read CFI data at the addresses given in tables
5 through 7. The system must write the CFI Exit command
to return to Read mode from the CFI Query mode.
Product Identification
The Product Identification mode identifies the device as the
SST39VF400 and manufacturer as SST. This mode may
be accessed by hardware or software operations. The
hardware operation is typically used by a programmer to
identify the correct algorithm for the SST39VF400. Users
may wish to use the Software Product Identification opera-
tion to identify the part (i.e., using the device code) when
using multiple manufacturers in the same socket. For
details, see Table 3 for hardware operation or Table 4 for
software operation, Figure 11 for the Software ID Entry and
Read timing diagram and Figure 18 for the Software ID
Entry command sequence flowchart.
T
ABLE
1: P
RODUCT
I
DENTIFICATION
T
ABLE
Address
Manufacturer’s Code
Device Code
0000H
0001H
Data
00BFH
2780H
342 PGM T1.0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Product Identification Mode Exit/CFI Mode Exit
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Software ID Exit command se-
quence, which returns the device to the Read operation.
This command may also be used to reset the device to the
Read mode after any inadvertent transient condition that
apparently causes the device to behave abnormally, e.g.,
not read correctly. Please note that the Software ID Exit/CFI
Exit command is ignored during an internal Program or
Erase operation. See Table 4 for software command codes,
Figure 13 for timing waveform and Figure 18 for a flowchart.
© 1999 Silicon Storage Technology, Inc.
3
342-06 7/99
4 Megabit Multi-Purpose Flash
SST39VF400
Advance Information
F
UNCTIONAL
B
LOCK
D
IAGRAM
4,194,304 bit
EEPROM
Cell Array
X-Decoder
A17 - A0
Address Buffer & Latches
Y-Decoder
CE#
OE#
WE#
DQ15 - DQ0
342 ILL B1.1
Control Logic
I/O Buffers and Data Latches
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
NC
NC
NC
NC
NC
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Standard Pinout
Top View
Die Up
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
NC
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
342 ILL1a.0
SST39VF400
F
IGURE
1: P
IN
A
SSIGNMENTS FOR
48-
PIN
TSOP P
ACKAGES
TOP
VIEW
6
A13 A12
A14
A10
NC
NC
A6
A2
A15
A11
NC
NC
A5
A1
A16
NC
DQ15 VSS
5
A9
A8
DQ7 DQ14 DQ13 DQ6
DQ5 DQ12 VDD DQ4
DQ2 DQ10 DQ11 DQ3
DQ0
A0
DQ8
CE#
DQ9 DQ1
OE# VSS
4
WE# NC
3
NC
NC
A17
A4
2
A7
1
A3
A B C D E F G H
SST39VF400
342 ILL2a.4
F
IGURE
2: P
IN
A
SSIGNMENTS FOR
48-
BALL
TFBGA
© 1999 Silicon Storage Technology, Inc.
4
342-06 7/99
4 Megabit Multi-Purpose Flash
SST39VF400
Advance Information
T
ABLE
2: P
IN
D
ESCRIPTION
Symbol
Pin Name
A
17
-A
0
Address Inputs
Functions
To provide memory addresses. During Sector-Erase A
17
-A
11
address
lines will select the sector. During Block-Erase A
17
-A
15
address lines will
select the block.
To output data during read cycles and receive input data during write
cycles. Data is internally latched during a write cycle. The outputs are in
tri-state when OE# or CE# is high.
To activate the device when CE# is low.
To gate the data output buffers.
To control the Write operations.
To provide 3-volt supply (2.7-3.6V)
Unconnected pins.
342 PGM T2.1
1
2
3
4
5
6
DQ
15
-DQ
0
Data Input/output
CE#
OE#
WE#
V
DD
Vss
NC
Chip Enable
Output Enable
Write Enable
Power Supply
Ground
No Connection
T
ABLE
3: O
PERATION
M
ODES
S
ELECTION
Mode
Read
Program
Erase
Standby
Write Inhibit
Product Identification
Hardware Mode
Software Mode
CE#
V
IL
V
IL
V
IL
V
IH
X
X
V
IL
V
IL
OE#
V
IL
V
IH
V
IH
X
V
IL
X
V
IL
V
IL
WE#
V
IH
V
IL
V
IL
X
X
V
IH
V
IH
V
IH
A9
A
IN
A
IN
X
X
X
X
V
H
A
IN
DQ
D
OUT
D
IN
X
High Z
High Z/ D
OUT
High Z/ D
OUT
Manufacturer Code (00BF)
Device Code (2780)
Address
A
IN
A
IN
Sector or Block address,
XXh for Chip-Erase
X
X
X
A
17
- A
1
= V
IL
, A
0
= V
IL
A
17
- A
1
= V
IL
, A
0
= V
IH
See Table 4
342 PGM T3.0
7
8
9
10
11
12
13
14
15
16
© 1999 Silicon Storage Technology, Inc.
5
342-06 7/99
