Integrated
Circuit
Systems, Inc.
ICSSSTUA32864B
25-Bit Configurable Registered Buffer for DDR2
Recommended Application:
•
DDR2 Memory Modules
•
Provides complete DDR DIMM solution with
ICS97U877
•
Ideal for DDR2 400, 533 and 667
Product Features:
•
25-bit 1:1 or 14-bit 1:2 configurable registered buffer
•
Supports SSTL_18 JEDEC specification on data
inputs and outputs
•
Supports LVCMOS switching levels on C0, C1 and
RESET# inputs
•
Low voltage operation
V
DD
= 1.7V to 1.9V
•
Available in 96 BGA package
•
Drop-in replacement for ICSSSTUA32866
•
Green packages available
Pin Configuration
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
2
3
4
5
6
96 Ball BGA
(Top View)
Truth Table
I nputs
RST#
H
H
H
H
H
H
H
H
H
H
H
H
L
DCS#
L
L
L
L
L
L
H
H
H
H
H
H
X or
Floating
CSR#
L
L
L
H
H
H
L
L
L
H
H
H
X or
Floating
L or H
X or
Floating
L or H
X or
Floating
L or H
L or H
L or H
L or H
L or H
L or H
CK
CK#
Dn,
DODT,
DCK E
L
H
X
L
H
X
L
H
X
L
H
X
X or
Floating
Qn
L
H
Q
0
L
H
Q
0
L
H
Q
0
Q
0
Q
0
Q
0
L
Outputs
QCS#
L
L
Q
0
L
L
Q
0
H
H
Q
0
H
H
Q
0
L
QODT,
QCKE
L
H
Q
0
L
H
Q
0
L
H
Q
0
L
H
Q
0
L
Ball Assignments
A
DCKE
B
D2
C
D3
D
DODT
E
D5
F
D6
G
NC
H
CK
J
CK#
K
D8
L
D9
NC
D15
D16
NC
D17
D18
RST#
DCS#
CSR#
D19
D20
D21
D22
D23
D24
D25
V
REF
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
V
REF
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
V
DD
QCKE
Q2
Q3
QODT
Q5
Q6
C1
QCS#
ZOH
Q8
Q9
Q10
Q11
Q12
Q13
Q14
NC
Q15
Q16
NC
Q17
Q18
C0
NC
ZOL
Q19
Q20
Q21
Q22
Q23
Q24
Q25
M
D10
N
D11
P
D12
R
D13
T
D14
1
2
3
4
5
6
1:1 Register (C0 = 0, C1 = 0)
1055A—01/28/05
ICSSSTUA32864B
Ball Assignments
A
DCKE
B
D2
C
D3
D
DODT
E
D5
F
D6
G
NC
H
CK
J
CK#
K
D8
L
D9
M
D10
N
D11
P
D12
R
D13
T
D14
1
NC
NC
NC
NC
NC
NC
RST#
DCS#
CSR#
NC
NC
NC
NC
NC
NC
NC
V
REF
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
V
REF
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
V
DD
QCKEA
Q2A
Q3A
QODTA
Q5A
Q6A
C1
QCSA#
ZOH
Q8A
Q9A
Q10A
Q11A
Q12A
Q13A
Q14A
QCKEB
Q2B
Q3B
QODTB
Q5B
Q6B
C0
QCSB#
ZOL
Q8B
Q9B
Q10B
Q11B
Q12B
Q13B
Q14B
Ball Assignments
A
D1
B
D2
C
D3
D
D4
E
D5
F
D6
G
NC
H
CK
J
CK#
K
D8
L
D9
NC
NC
NC
NC
NC
NC
RST#
DCS#
CSR#
NC
NC
NC
NC
NC
NC
NC
V
REF
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
V
REF
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
V
DD
Q1A
Q2A
Q3A
Q4A
Q5A
Q6A
C1
QCSA#
ZOH
Q8A
Q9A
Q10A
QODTA
Q12A
Q13A
QCKEA
Q1B
Q2B
Q3B
Q4B
Q5B
Q6B
C0
QCSB#
ZOL
Q8B
Q9B
Q10B
QODTB
Q12B
Q13B
QCKEB
M
D10
N
DODT
P
D12
R
D13
T
DCKE
1
2
3
4
5
6
2
3
4
5
6
1:2 Register A (C0 = 0, C1 = 1)
General Description
1:2 Register B (C0 = 1, C1 = 1)
This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation.
All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All
outputs are 1.8-V CMOS drivers that have been optimized to drive the DDR-II DIMM load.
ICSSSTUA32864B
operates
from a differential clock (CK and CK#). Data are registered at the crossing of CK going high, and CK# going low.
The C0 input controls the pinout configuration of the 1:2 pinout from A configuration (when low) to B configuration (when
high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high).
The device supports low-power standby operation. When the reset input (RST#) is low, the differential input receivers
are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when
RST# is low all registers are reset, and all outputs are forced low. The LVCMOS RST# and Cn inputs must always be
held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied,
RST# must be held in the low state during power up.
In the DDR-II RDIMM application, RST# is specified to be completely asynchronous with respect to CK and CK#.
Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared
and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when
coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers.
As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RST# until
the input receivers are fully enabled, the design of the
ICSSSTUA32864B
must ensure that the outputs will remain
low, thus ensuring no glitches on the output.
The device monitors both DCS# and CSR# inputs and will gate the Qn outputs from changing states when both DCS#
and CSR# inputs are high. If either DCS# or CSR# input is low, the Qn outputs will function normally. The RST input
has priority over the DCS# and CSR# control and will force the outputs low. If the DCS#-control functionality is not
desired, then the CSR# input can be hardwired to ground, in which case, the setup-time requirement for DCS# would
be the same as for the other D data inputs. Package options include 96-ball LFBGA (MO-205CC).
1055A—01/28/05
2
ICSSSTUA32864B
Ball Assignment
Terminal Name
GND
V
DD
V
REF
Z
OH
Z
OL
CK
CK#
C0, C1
RST#
CSR#, DCS#
D1 - D25
DODT
DCKE
Q1 - Q25
QCS#
QODT
QCKE
Ground
Power supply voltage
Input reference voltage
Reserved for future use
Reserved for future use
Positive master clock input
Negative master clock input
Configuration control inputs
Asynchronous reset input - resets registers and disables V
REF
data and
clock differential-input receivers
Description
Electrical
Characteristics
Ground input
1.8V nominal
0.9V nominal
Input
Input
Differential input
Differential input
LVCMOS inputs
LV C M O S i n p u t
Chip select inputs - disables D1 - D24 outputs switching when both inputs
SSTL_18 input
are high
Data input - clock in on the crossing of the rising edge of CK and the
falling edge of CK#
The outputs of this register bit will not be suspended by the DCS# and
CSR# control
The outputs of this register bit will now be suspended by the DCS# and
CSR# control
Data ouputs that are suspended by the DCS# and CSR# control
Data output that will not be suspended by the DCS# and CSR# control
Data output that will not be suspended by the DCS# and CSR# control
Data output that will not be suspended by the DCS# and CSR# control
SSTL_18 input
SSTL_18 input
SSTL_18 input
1.8V CMOS
1.8V CMOS
1.8V CMOS
1.8V CMOS
1055A—01/28/05
3
ICSSSTUA32864B
Block Diagram for 1:1 mode (positive logic)
RST#
CK
CK#
V
REF
DCKE
D
C1
R
QCKEA
DODT
D
C1
R
QODTA
DCS#
1D
C1
R
QCSA#
CSR#
D1
0
1
1D
C1
R
Q1B
*
Q1A
To 21 Other Channels
*Note: Disabled in 1:1 configuration
1055A—01/28/05
4
ICSSSTUA32864B
Block Diagram for 1:2 mode (positive logic)
RST#
CK
CK#
V
REF
DCKE
1D
C1
R
QCKEA
QCKEB*
DODT
1D
C1
R
QODTA
QODTB*
DCS#
1D
C1
R
QCSA#
QCSB#*
CSR#
D1
0
1
1D
C1
R
Q1B
*
Q1A
To 10 Other Channels
*Note: Disabled in 1:1 configuration
1055A—01/28/05
5
RF/无线
