ST16C554/554D
2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO
JUNE 2006
REV. 4.0.1
GENERAL DESCRIPTION
The ST16C554/554D (554) is a quad Universal
Asynchronous Receiver and Transmitter (UART) with
16 bytes of transmit and receive FIFOs, selectable
receive FIFO trigger levels and data rates of up to 1.5
Mbps. Each UART has a set of registers that provide
the user with operating status and control, receiver
error indications, and modem serial interface
controls. An internal loopback capability allows
onboard diagnostics. The 554 is available in a 64-pin
LQFP and a 68-pin PLCC package. The 64-pin
package only offers the 16 mode interface, but the
68-pin package offers an additional 68 mode
interface which allows easy integration with Motorola
processors. The ST16C554CQ64 (64-pin) offers
three
state
interrupt
output
while
the
ST16C554DCQ64 provides continuous interrupt
output. The 554 combines the package interface
modes of the 16C554 and 68C554 on a single
integrated chip.
FEATURES
•
Pin-to-pin compatible with the industry standard
ST16C454,
ST68C454,
ST68C554,
TL16C554A and Philips’ SC16C554B
TI’s
•
Intel or Motorola Data Bus Interface select
•
Four independent UART channels
■
■
■
■
■
■
■
Register Set Compatible to 16C550
Data rates of up to 1.5 Mbps at 5 V
Data rates of up to 500 Kbps at 3.3V
16 byte Transmit FIFO
16 byte Receive FIFO with error tags
4 Selectable RX FIFO Trigger Levels
Full modem interface
•
2.97V to 5.5V supply operation
•
Crystal oscillator or external clock input
APPLICATIONS
•
Portable Appliances
•
Telecommunication Network Routers
•
Ethernet Network Routers
•
Cellular Data Devices
•
Factory Automation and Process Controls
F
IGURE
1. ST16C554 B
LOCK
D
IAGRAM
A2:A0
D7:D0
IOR#
IOW#
CSA#
CSB#
CSC#
CSD#
INTA
INTB
INTC
INTD
TXRDY# A-D
RXRDY# A-D
Reset
16/ 68#
INTSEL
UART Channel D
(same as Channel A)
UART Channel A
UART 16 Byte TX FIFO
Regs
IR
TX & RX
ENDEC
BRG
16 Byte RX FIFO
UART Channel B
(same as Channel A)
UART Channel C
(same as Channel A)
2.97 V to 5.5 V VCC
GND
TXA, RXA, IRTXA, DTRA#,
DSRA#, RTSA#, CTSA#,
CDA#, RIA#
Data Bus
Interface
TXB, RXB, IRTXB, DTRB#,
DSRB#, RTSB#, CTSB#,
CDB#, RIB#
TXC, RXC, IRTXC, DTRC#,
DSRC#, RTSC#, CTSC#,
CDC#, RIC#
TXD, RXD, IRTXD, DTRD#,
DSRD#, RTSD#, CTSD#,
CDD#, RID#
XTAL1
XTAL2
Crystal Osc / Buffer
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
ST16C554/554D
2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO
F
IGURE
2. P
IN
O
UT
A
SSIGNMENT
INTSEL
REV. 4.0.1
RIA#
RIA#
CDD#
CDA#
RID#
GND
RXD
VCC
RXA
D7
D6
D5
D4
D3
D2
D1
D0
68
67
66
65
64
63
62
68
67
66
65
64
63
62
63
9
8
7
6
5
4
3
2
1
DSRA#
CTSA#
DTRA#
VCC
RTSA#
INTA
CSA#
TXA
IOW#
TXB
CSB#
INTB
RTSB#
GND
DTRB#
CTSB#
DSRB#
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
60
59
58
57
56
55
DSRD#
CTSD#
DTRD#
GND
RTSD#
INTD
CSD#
TXD
IOR#
TXC
CSC#
INTC
RTSC#
VCC
DTRC#
CTSC#
DSRC#
DSRA#
CTSA#
DTRA#
VCC
RTSA#
IRQ#
CS#
TXA
R/W#
TXB
A3
N.C.
RTSB#
GND
DTRB#
CTSB#
DSRB#
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
63
9
8
7
6
5
4
3
2
1
CDD#
CDA#
RID#
GND
GND
VCC
RXD
RXA
D7
D6
D5
D4
D3
D2
D1
D0
60
59
58
57
56
55
DSRD#
CTSD#
DTRD#
GND
RTSD#
N.C.
N.C.
TXD
N.C.
TXC
A4
N.C.
RTSC#
VCC
DTRC#
CTSC#
DSRC#
ST16C554
68-pin PLCC
Intel Mode
(16/68# pin connected to VCC)
54
53
52
51
50
49
48
47
46
45
44
ST16C554
68-pin PLCC
Motorola Mode
(16/68# pin connected to GND)
54
53
52
51
50
49
48
47
46
45
44
16/68#
CDB#
TXRDY#
RXRDY#
RESET
XTAL1
XTAL2
TXRDY#
16/68#
RXRDY#
RESET
XTAL1
XTAL2
CDC#
CDD#
RIA#
68
67
66
65
64
63
62
64
60
56
54
52
51
62
61
59
57
55
58
50
63
53
49
DSRA#
CTSA#
DTRA#
VCC
RTSA#
INTA
CSA#
TXA
IOW#
TXB
CSB#
INTB
RTSB#
GND
DTRB#
CTSB#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
21
29
23
26
30
31
22
25
27
28
32
20
17
18
19
24
48
47
46
45
44
43
DSRD #
CTSD #
DTRD #
GND
RTSD #
INTD
CSD #
TXD
IOR#
TXC
CSC #
INTC
RTSC #
VCC
DTRC #
CTSC #
DSRA#
CTSA#
DTRA#
VCC
RTSA#
IRQ#
CS#
TXA
R/W#
TXB
A3
N.C.
RTSB#
GND
DTRB#
CTSB#
DSRB#
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
63
9
8
7
6
5
4
3
2
1
CDD#
CDA#
CDA#
GND
RID#
RIA#
VCC
RXD
RXA
RID#
GND
GND
VCC
RXD
RXA
D7
D6
D5
D4
D2
D3
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
CDC#
60
59
58
57
56
55
CDB#
RIC#
RIB#
RIC#
RIB#
GND
RXB
GND
VCC
VCC
RXC
RXC
A2
A1
RXB
A2
A1
A0
A0
DSRD#
CTSD#
DTRD#
GND
RTSD#
N.C.
N.C.
TXD
N.C.
TXC
A4
N.C.
RTSC#
VCC
DTRC#
CTSC#
DSRC#
ST16C554/554D
64-pin TQFP
Intel Mode Only
42
41
40
39
38
37
36
35
34
33
ST68C554
68-pin PLCC
Motorola Mode Only
54
53
52
51
50
49
48
47
46
45
44
RIB#
DSRB#
CDC#
CDB#
RIC#
A1
A0
RESET
DSRC#
A2
XTAL1
XTAL2
GND
VCC
RXC
RXB
CDB#
TXRDY#
RXRDY#
RESET
XTAL1
XTAL2
ORDERING INFORMATION
P
ART
N
UMBER
ST16C554CQ64
ST16C554DCQ64
ST16C554DIQ64
ST16C554DCJ68
ST16C554DIJ68
ST68C554CJ68
ST68C554IJ68
P
ACKAGE
64-Lead LQFP
64-Lead LQFP
64-Lead LQFP
68-Lead PLCC
68-Lead PLCC
68-Lead PLCC
68-Lead PLCC
O
PERATING
T
EMPERATURE
R
ANGE
0°C to +70°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
D
EVICE
S
TATUS
Active
Active
Active
Active
Active
Active
Active
2
CDC#
RIC#
GND
RIB#
RXB
GND
VCC
RXC
A2
A1
A0
ST16C554/554D
REV. 4.0.1
2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO
PIN DESCRIPTIONS
Pin Description
N
AME
64-LQFP 68-PLCC
T
YPE
P
IN
#
P
IN
#
D
ESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
IOR#
(VCC)
22
23
24
60
59
58
57
56
55
54
53
40
32
33
34
5
4
3
2
1
68
67
66
52
I
Address data lines [2:0]. These 3 address lines select one of the internal regis-
ters in UART channel A-D during a data bus transaction.
I/O
Data bus lines [7:0] (bidirectional).
I
When 16/68# pin is HIGH, the Intel bus interface is selected and this input
becomes read strobe (active low). The falling edge instigates an internal read
cycle and retrieves the data byte from an internal register pointed by the address
lines [A2:A0], puts the data byte on the data bus to allow the host processor to
read it on the rising edge.
When 16/68# pin is LOW, the Motorola bus interface is selected and this input is
not used and should be connected to VCC.
When 16/68# pin is HIGH, it selects Intel bus interface and this input becomes
write strobe (active low). The falling edge instigates the internal write cycle and
the rising edge transfers the data byte on the data bus to an internal register
pointed by the address lines.
When 16/68# pin is LOW, the Motorola bus interface is selected and this input
becomes read (HIGH) and write (LOW) signal.
When 16/68# pin is HIGH, this input is chip select A (active low) to enable chan-
nel A in the device.
When 16/68# pin is LOW, this input becomes the chip select (active low) for the
Motorola bus interface.
When 16/68# pin is HIGH, this input is chip select B (active low) to enable chan-
nel B in the device.
When 16/68# pin is LOW, this input becomes address line A3 which is used for
channel selection in the Motorola bus interface.
When 16/68# pin is HIGH, this input is chip select C (active low) to enable chan-
nel C in the device.
When 16/68# pin is LOW, this input becomes address line A4 which is used for
channel selection in the Motorola bus interface.
When 16/68# pin is HIGH, this input is chip select D (active low) to enable chan-
nel D in the device.
When 16/68# pin is LOW, this input is not used and should be connected VCC.
IOW#
(R/W#)
9
18
I
CSA#
(CS#)
7
16
I
CSB#
(A3)
11
20
I
CSC#
(A4)
38
50
I
CSD#
(VCC)
42
54
I
3
ST16C554/554D
2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO
Pin Description
N
AME
INTA
(IRQ#)
64-LQFP 68-PLCC
T
YPE
P
IN
#
P
IN
#
6
15
D
ESCRIPTION
REV. 4.0.1
O
When 16/68# pin is HIGH for Intel bus interface, this ouput becomes channel A
(OD) interrupt output. The output state is defined by the user and through the soft-
ware setting of MCR[3]. INTA is set to the active mode when MCR[3] is set to a
logic 1. INTA is set to the three state mode when MCR[3] is set to a logic 0
(default). See MCR[3].
When 16/68# pin is LOW for Motorola bus interface, this output becomes device
interrupt output (active low, open drain). An external pull-up resistor is required
for proper operation.
O
When 16/68# pin is HIGH for Intel bus interface, these ouputs become the inter-
rupt outputs for channels B, C, and D. The output state is defined by the user
through the software setting of MCR[3]. The interrupt outputs are set to the
active mode when MCR[3] is set to a logic 1 and are set to the three state mode
when MCR[3] is set to a logic 0 (default). See MCR[3].
When 16/68# pin is LOW for Motorola bus interface, these outputs are unused
and will stay at logic zero level. Leave these outputs unconnected.
Interrupt Select (active high, input with internal pull-down).
When 16/68# pin is HIGH for Intel bus interface, this pin can be used in conjunc-
tion with MCR bit-3 to enable or disable the INT A-D pins or override MCR bit-3
and enable the interrupt outputs. Interrupt outputs are enabled continuously
when this pin is HIGH. MCR bit-3 enables and disables the interrupt output
pins. In this mode, MCR bit-3 is set to a logic 1 to enable the continuous output.
See MCR bit-3 description for full detail. This pin must be LOW in the Motorola
bus interface mode. For the 64 pin packages, this pin is bonded to VCC inter-
nally in the ST16C554DCQ64 so the INT outputs operate in the continuous
interrupt mode. This pin is bonded to GND internally in the ST16C554CQ64 and
therefore requires setting MCR bit-3 for enabling the interrupt output pins.
Transmitter Ready (active low). This output is a logically ANDed status of
TXRDY# A-D. See
Table 5.
If this output is unused, leave it unconnected.
Receiver Ready (active low). This output is a logically ANDed status of RXRDY#
A-D. See
Table 5.
If this output is unused, leave it unconnected.
INTB
INTC
INTD
(N.C.)
12
37
43
21
49
55
INTSEL
-
65
I
TXRDY#
RXRDY#
-
-
39
38
O
O
MODEM OR SERIAL I/O INTERFACE
TXA
TXB
TXC
TXD
RXA
RXB
RXC
RXD
RTSA#
RTSB#
RTSC#
RTSD#
CTSA#
CTSB#
CTSC#
CTSD#
8
10
39
41
62
20
29
51
5
13
36
44
2
16
33
47
17
19
51
53
7
29
41
63
14
22
48
56
11
25
45
59
O
UART channels A-D Transmit Data and infrared transmit data. In this mode, the
TX signal will be HIGH during reset, or idle (no data).
I
UART channel A-D Receive Data. Normal receive data input must idle HIGH.
O
UART channels A-D Request-to-Send (active low) or general purpose output. If
these outputs are not used, leave them unconnected.
I
UART channels A-D Clear-to-Send (active low) or general purpose input. These
inputs should be connected to VCC when not used.
4
ST16C554/554D
REV. 4.0.1
2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO
Pin Description
N
AME
DTRA#
DTRB#
DTRC#
DTRD#
DSRA#
DSRB#
DSRC#
DSRD#
CDA#
CDB#
CDC#
CDD#
RIA#
RIB#
RIC#
RID#
64-LQFP 68-PLCC
T
YPE
P
IN
#
P
IN
#
3
15
34
46
1
17
32
48
64
18
31
49
63
19
30
50
12
24
46
58
10
26
44
60
9
27
43
61
8
28
42
62
O
D
ESCRIPTION
UART channels A-D Data-Terminal-Ready (active low) or general purpose out-
put. If these outputs are not used, leave them unconnected.
I
UART channels A-D Data-Set-Ready (active low) or general purpose input. This
input should be connected to VCC when not used. This input has no effect on
the UART.
I
UART channels A-D Carrier-Detect (active low) or general purpose input. This
input should be connected to VCC when not used. This input has no effect on
the UART.
I
UART channels A-D Ring-Indicator (active low) or general purpose input. This
input should be connected to VCC when not used. This input has no effect on
the UART.
ANCILLARY SIGNALS
XTAL1
XTAL2
16/68#
25
26
-
35
36
31
I
O
I
Crystal or external clock input.
Crystal or buffered clock output.
Intel or Motorola Bus Select (input with internal pull-up).
When 16/68# pin is HIGH, 16 or Intel Mode, the device will operate in the Intel
bus type of interface.
When 16/68# pin is LOW, 68 or Motorola mode, the device will operate in the
Motorola bus type of interface.
Motorola bus interface is not available on the 64 pin package.
When 16/68# pin is HIGH for Intel bus interface, this input becomes the Reset
pin (active high). In this case, a 40 ns minimum HIGH pulse on this pin will
reset the internal registers and all outputs. The UART transmitter output will be
held HIGH, the receiver input will be ignored and outputs are reset during reset
period (Table
13).
When 16/68# pin is at LOW for Motorola bus interface, this
input becomes Reset# pin (active low). This pin functions similarly, but instead
of a HIGH pulse, a 40 ns minimum LOW pulse will reset the internal registers
and outputs.
Motorola bus interface is not available on the 64 pin package.
2.97V to 5.5V power supply.
Power supply common, ground.
No Connection. These pins are not used in either the Intel or Motorola bus
modes.
RESET
(RESET#)
27
37
I
VCC
GND
N.C.
4, 21, 35,
52
14, 28,
45, 61
-
13, 30,
47, 64
6, 23, 40,
57
-
Pwr
Pwr
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
5
