ST24LC21B, ST24LW21
ST24FC21, ST24FC21B, ST24FW21
1 Kbit (x8) Dual Mode Serial EEPROM
for VESA PLUG & PLAY
1 MILLION ERASE/WRITE CYCLES
40 YEARS DATA RETENTION
3.6V to 5.5V or 2.5V to 5.5V SINGLE SUPPLY
VOLTAGE
HARDWARE WRITE CONTROL (ST24LW21
and ST24FW21)
TTL SCHMITT-TRIGGER on VCLK INPUT
100k / 400k Hz COMPATIBILITY with the I
2
C
BUS BIT TRANSFER RANGE
TWO WIRE SERIAL INTERFACE I
2
C BUS
COMPATIBLE
I
2
C PAGE WRITE (up to 8 Bytes)
I
2
C BYTE, RANDOM and SEQUENTIAL READ
MODES
SELF TIMED PROGRAMMING CYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD/LATCH UP
PERFORMANCES
ERROR RECOVERY MECHANISM
(ST24FC21 and ST24FW21) VESA 2
COMPATIBLE
DESCRIPTION
The ST24LC21B, ST24LW21, ST24FC21,
ST24FC21B and ST24FW21 are 1K bit electrically
erasable programmable memory (EEPROM), or-
ganized in 128x8 bits. In the text, products are
referred as ST24xy21, where "x" is either "L" for
VESA 1 or "F" for VESA 2 compatible memories
and where "y" indicates the Write Control pin con-
nection: "C" means WC on pin 7 and "W" means
WC on pin 3.
8
1
PSDIP8 (B)
0.25mm Frame
8
1
SO8 (M)
150mil Width
Figure 1. Logic Diagram
VCC
SCL
VCLK
WC
ST24xy21
SDA
Table 1. Signal Names
SDA
SCL
V
CC
V
SS
VCLK
WC
Serial Data Address Input/Output
Serial Clock (I C mode)
Supply Voltage
Ground
Clock Transmit only mode
Write Control
Note:
WC signal is only available for ST24LW21 and ST24FW21
products.
2
VSS
AI01741
June 2002
1/22
ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21
Figure 2A. DIP Pin Connections
Figure 2B. SO Pin Connections
ST24LC21B
NC
NC
NC
VSS
1
2
3
4
8
7
6
5
AI01742
ST24LC21B
VCC
VCLK
SCL
SDA
NC
NC
NC
VSS
1
2
3
4
8
7
6
5
AI01743
VCC
VCLK
SCL
SDA
Warning:
NC = Not Connected.
Warning:
NC = Not Connected.
Figure 2C. DIP Pin Connections
Figure 2D. SO Pin Connections
ST24FC21
ST24FC21B
NC
NC
DU
VSS
1
2
3
4
8
7
6
5
AI01744
ST24FC21
ST24FC21B
VCC
VCLK
SCL
SDA
NC
NC
DU
VSS
1
2
3
4
8
7
6
5
AI01745
VCC
VCLK
SCL
SDA
Warning:
NC = Not Connected. DU = Don’t Use, must
be left open or connected to V
CC
or V
SS
.
Warning:
NC = Not Connected. DU = Don’t Use, must
be left open or connected to V
CC
or V
SS
.
Figure 2E. DIP Pin Connections
Figure 2F. SO Pin Connections
ST24FW21
ST24LW21
NC
NC
WC
VSS
1
2
3
4
8
7
6
5
AI01746
ST24FW21
ST24LW21
VCC
VCLK
SCL
SDA
NC
NC
WC
VSS
1
2
3
4
8
7
6
5
AI01747
VCC
VCLK
SCL
SDA
Warning:
NC = Not Connected.
Warning:
NC = Not Connected.
2/22
ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21
Table 2. Absolute Maximum Ratings
(1)
Symbol
T
A
T
STG
T
LEAD
V
IO
V
CC
V
ESD
Parameter
Ambient Operating Temperature
Storage Temperature
Lead Temperature, Soldering
Input or Output Voltages
Supply Voltage
Electrostatic Discharge Voltage (Human Body model)
Electrostatic Discharge Voltage (Machine model)
(3)
(2)
Value
–40 to 85
–65 to 150
Unit
°C
°C
°C
V
V
V
V
(SO8 package)
(PSDIP8 package)
40 sec
10 sec
215
260
–0.3 to 6.5
–0.3 to 6.5
4000
500
Notes:
1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
2. MIL-STD-883C, 3015.7 (100pF, 1500
Ω).
3. EIAJ IC-121 (Condition C) (200pF, 0
Ω).
Table 3A. Device Select Code (ST24LC21B, ST24LW21, ST24FC21 and ST24FW21)
Device Code
Bit
Device Select
b7
1
b6
0
b5
1
b4
0
b3
X
Chip Enable
b2
X
b1
X
RW
b0
RW
Note:
The MSB b7 is sent first.
X = 0 or 1.
Table 3B. Device Select Code (ST24FC21B)
Device Code
Bit
Device Select
b7
1
b6
0
b5
1
b4
0
b3
0
Chip Enable
b2
0
b1
0
RW
b0
RW
Note:
The MSB b7 is sent first.
X = 0 or 1.
DESCRIPTION
(cont’d)
The ST24xy21 can operate in two modes: Trans-
mit-Only mode and I
2
C bidirectional mode. When
powered, the device is in Transmit-Only mode with
EEPROM data clocked out from the rising edge of
the signal applied on VCLK.
The device will switch to the I
2
C bidirectional mode
upon the falling edge of the signal applied on SCL
pin. When in I
2
C mode, the ST24LC21B (or the
ST24LW21) cannot switch back to the Transmit
Only mode (except when the power supply is re-
moved). For the ST24FC21, ST24FC21B (or the
ST24FW21), after the falling edge of SCL, the
memory enter in a transition state which allowed to
switch back to the Transmit-Only mode if no valid
I
2
C activity is observed. Both Plastic Dual-in-Line
and Plastic Small Outline packages are available.
Transmit Only Mode
After a Power-up, the ST24xy21 is in the Transmit
Only mode. A proper initialization sequence (see
Figure 3) must supply nine clock pulses on the
VCLK pin (in order to internally synchronize the
device). During this initialization sequence, the
SDA pin is in high impedance. On the rising edge
of the tenth pulse applied on VCLK pin, the device
will output the first bit of byte located at address 00h
(most significant bit first).
3/22
ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21
Figure 3. Transmit Only Mode Waveforms
VCC
SCL
SDA
tVPU
VCLK
1
2
8
9
10
Bit 7
Bit 6
11
VCC
SCL
SDA
Bit 6
Bit 5
Bit 4
Bit 0
Bit 7
Bit 6
VCLK
12
13
17
18
19
20
AI01501
Table 4. I
2
C Operating Modes
Mode
RW
bit
ST24LC21B
ST24FC21
ST24FC21B
VCLK
X
X
X
X
V
IH
V
IH
ST24LW21
ST24FW21
WC
X
X
X
X
V
IH
V
IH
1 to 128
1
8
Bytes
Initial Sequence
Current Address
Read
Random Address
Read
Sequential Read
Byte Write
Page Write
Note:
X = V
IH
or V
IL
’1’
’0’
’1’
’1’
’0’
’0’
1
1
START, Device Select, RW = ’1’
START, Device Select, RW = ’0’, Address,
reSTART, Device Select, RW = ’1’
Similar to Current or Random Mode
START, Device Select, RW = ’0’
START, Device Select, RW = ’0’
4/22
ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21
Figure 4. Transition from Transmit Only (DDC1) to Bi-directional (DDC2B) Mode Waveforms
Transmit Only Mode
- Temporary Bi-Directional Mode
(ST24FC21 and ST24FW21)
- Locked Bi-Directional Mode
(ST24LC21B and ST24LW21)
2
8
9
- Locked Bi-Directional
Mode (ST24FC21
and ST24FW21)
SCL
1
SDA
MSB
ACK
VCLK
START
CONDITION
AI01892
A byte is clocked out (on SDA pin) with nine clock
pulses on VCLK: 8 clock pulses for the data byte
and one extra clock pulse for a Don’t Care bit.
As long as the SCL pin is held high, each byte of
the memory array is transmitted serially on the SDA
pin with an automatic address increment.
When the last byte is transmitted, the address
counter will roll-over to location 00h.
I
2
C Bidirectional Mode
The ST24xy21 can be switched from Transmit Only
mode to I
2
C Bidirectional mode by applying a valid
high to low transition on the SCL pin (see Figure 4).
– When the ST24LC21B (or the ST24FC21 or
the ST24FC21B) is in the I
2
C Bidirectional
mode, the VCLK input (pin 7) enables (or inhib-
its) the execution of any write instruction: if
VCLK = 1, write instructions are executed; if
VCLK = 0, write instructions are not executed.
– When the ST24LW21 (or the ST24FW21) is in
the I
2
C Bidirectional mode, the Write Control
(WC on pin 3) input enables (or inhibits) the
execution of any write instruction: if WC = 1,
write instructions are executed;if WC = 0,
write instructions are not executed.
The ST24xy21 is compatible with the I
2
C standard,
two wire serial interface which uses a bidirectional
data bus and serial clock. The ST24xy21 carries a
built-in 4 bit, unique device identification code
(1010) named Device Select code corresponding
to the I
2
C bus definition. The ST24LC21B carries a
unique device identification code (1010.0000 RW)
named Device Select code corresponding to the
I
2
C bus definition.
The ST24xy21 behaves as a slave device in the
I
2
C protocol with all memory operations synchro-
nized by the serial clock SCL. Read and write
operations are initiated by a START condition gen-
erated by the bus master. The START condition is
followed by a stream of 7 bits, plus one read/write
bit and terminated by an acknowledge bit.
When data is written into the memory, the
ST24xy21 responds to the 8 bits received by as-
serting an acknowledge bit during the 9th bit time.
When data is read by the bus master, it must
acknowledge the receipt of the data bytes in the
same way. Data transfers are terminated with a
STOP condition (see READ and WRITE descrip-
tions in the following pages).
Power On Reset: V
CC
lock out write protect
In order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is implemented. Until the V
CC
voltage has reached the POR threshold value, the
internal reset is active, all operations are disabled
and the device will not respond to any command.
In the same way, when V
CC
drops down from the
operating voltage to below the POR threshold
value, all operations are disabled and the device
will not respond to any command. A stable V
CC
must be applied before applying any logic signal.
Error Recovery Modes available in the
ST24FC21, ST24FC21B and the ST24FW21
5/22
