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ST24LC21B, ST24LW21

ST24FC21, ST24FW21

1 Kbit (x8) Dual Mode Serial EEPROM

for VESA PLUG & PLAY

1 MILLION ERASE/WRITE CYCLES

40 YEARS DATA RETENTION

3.6V to 5.5V SINGLE SUPPLY VOLTAGE

HARDWARE WRITE CONTROL (ST24LW21

and ST24FW21)

TTL SCHMITT-TRIGGER on VCLK INPUT

100k / 400k Hz COMPATIBILITY with the I

BUS BIT TRANSFER RANGE

TWO WIRE SERIAL INTERFACE I

C BUS

COMPATIBLE

C PAGE WRITE (up to 8 Bytes)

C BYTE, RANDOM and SEQUENTIAL READ

MODES

SELF TIMED PROGRAMMING CYCLE

AUTOMATIC ADDRESS INCREMENTING

ENHANCED ESD/LATCH UP

PERFORMANCES

ERROR RECOVERY MECHANISM

(ST24FC21 and ST24FW21) VESA 2

COMPATIBLE

DESCRIPTION

The ST24LC21B, ST24LW21, ST24FC21 and

ST24FW21 are 1K bit electrically erasable pro-

grammable memory (EEPROM), organized in

128x8 bits. In the text, products are referred as

ST24xy21, where "x" is either "L" for VESA 1 or "F"

for VESA 2 compatible memories and where "y"

indicates the Write Control pin connection: "C"

means WC on pin 7 and "W" means WC on pin 3.

Table 1. Signal Names

SDA

SCL

VCLK

Serial Data Address Input/Output

Serial Clock (I

C mode)

Supply Voltage

Ground

Clock Transmit only mode

Write Control

Note:

WC signal is only available for ST24LW21 and ST24FW21

products.

PSDIP8 (B)

0.25mm Frame

SO8 (M)

150mil Width

Figure 1. Logic Diagram

VCC

SCL

VCLK

ST24xy21

SDA

VSS

AI01741

January 1999

1/21

ST24LC21B, ST24LW21, ST24FC21, ST24FW21

Figure 2A. DIP Pin Connections

Figure 2B. SO Pin Connections

ST24LC21B

VSS

AI01742

ST24LC21B

VCC

VCLK

SCL

SDA

VSS

AI01743

VCC

VCLK

SCL

SDA

Warning:

NC = Not Connected.

Warning:

NC = Not Connected.

Figure 2C. DIP Pin Connections

Figure 2D. SO Pin Connections

ST24FC21

VSS

AI01744

ST24FC21

VCC

VCLK

SCL

SDA

VSS

AI01745

VCC

VCLK

SCL

SDA

Warning:

NC = Not Connected. DU = Don’t Use, must

be left open or connected to V

or V

Warning:

NC = Not Connected. DU = Don’t Use, must

be left open or connected to V

or V

Figure 2E. DIP Pin Connections

Figure 2F. SO Pin Connections

ST24FW21

ST24LW21

VSS

AI01746

ST24FW21

ST24LW21

VCC

VCLK

SCL

SDA

VSS

AI01747

VCC

VCLK

SCL

SDA

Warning:

NC = Not Connected.

Warning:

NC = Not Connected.

2/21

ST24LC21B, ST24LW21, ST24FC21, ST24FW21

Table 2. Absolute Maximum Ratings

(1)

Symbol

STG

LEAD

ESD

Parameter

Ambient Operating Temperature

Storage Temperature

Lead Temperature, Soldering

Input or Output Voltages

Supply Voltage

Electrostatic Discharge Voltage (Human Body model)

(2)

Electrostatic Discharge Voltage (Machine model)

(3)

(SO8 package)

(PSDIP8 package)

40 sec

10 sec

Value

–40 to 85

–65 to 150

215

260

–0.3 to 6.5

4000

500

Unit

°C

Notes:

1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"

may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other

conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum

Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other

relevant quality documents.

2. MIL-STD-883C, 3015.7 (100pF, 1500

Ω).

3. EIAJ IC-121 (Condition C) (200pF, 0

Ω).

Table 3. Device Select Code

Device Code

Bit

Device Select

Chip Enable

Note:

The MSB b7 is sent first.

X = 0 or 1.

DESCRIPTION

(cont’d)

The ST24xy21 can operate in two modes: Trans-

mit-Only mode and I

C bidirectional mode. When

powered, the device is in Transmit-Only mode with

EEPROM data clocked out from the rising edge of

the signal applied on VCLK.

The device will switch to the I

C bidirectional mode

upon the falling edge of the signal applied on SCL

pin. When in I

C mode, the ST24LC21B (or the

ST24LW21) cannot switch back to the Transmit

Only mode (except when the power supply is re-

moved). For the ST24FC21 (or the ST24FW21),

after the falling edge of SCL, the memory enter in

a transition state which allowed to switch back to

the Transmit-Only mode if no valid I

C activity is

observed. The device operates with a power supply

value as low as +3.6V. Both Plastic Dual-in-Line

and Plastic Small Outline packages are available.

Transmit Only Mode

After a Power-up, the ST24xy21 is in the Transmit

Only mode. A proper initialization sequence (see

Figure 3) must supply nine clock pulses on the

VCLK pin (in order to internally synchronize the

device). During this initialization sequence, the

SDA pin is in high impedance. On the rising edge

of the tenth pulse applied on VCLK pin, the device

will output the first bit of byte located at address 00h

(most significant bit first).

A byte is clocked out (on SDA pin) with nine clock

pulses on VCLK: 8 clock pulses for the data byte

and one extra clock pulse for a Don’t Care bit.

As long as the SCL pin is held high, each byte of

the memory array is transmitted serially on the SDA

pin with an automatic address increment.

When the last byte is transmitted, the address

counter will roll-over to location 00h.

3/21

ST24LC21B, ST24LW21, ST24FC21, ST24FW21

Figure 3. Transmit Only Mode Waveforms

VCC

SCL

SDA

tVPU

VCLK

Bit 7

Bit 6

VCC

SCL

SDA

Bit 6

Bit 5

Bit 4

Bit 0

Bit 7

Bit 6

VCLK

AI01501

Table 4. I

C Operating Modes

Mode

Current Address

Read

Random Address

Read

Sequential Read

Byte Write

Page Write

Note:

X = V

or V

bit

’1’

’0’

’1’

’0’

ST24LC21B

ST24FC21

VCLK

ST24LW21

ST24FW21

Bytes

Initial Sequence

1 to 128

START, Device Select, RW = ’1’

START, Device Select, RW = ’0’, Address,

reSTART, Device Select, RW = ’1’

Similar to Current or Random Mode

START, Device Select, RW = ’0’

4/21

ST24LC21B, ST24LW21, ST24FC21, ST24FW21

Figure 4. Transition from Transmit Only (DDC1) to Bi-directional (DDC2B) Mode Waveforms

Transmit Only Mode

- Temporary Bi-Directional Mode

(ST24FC21 and ST24FW21)

- Locked Bi-Directional Mode

(ST24LC21B and ST24LW21)

- Locked Bi-Directional

Mode (ST24FC21

and ST24FW21)

SCL

SDA

MSB

ACK

VCLK

START

CONDITION

AI01892

C Bidirectional Mode

The ST24xy21 can be switched from Transmit Only

mode to I

C Bidirectional mode by applying a valid

high to low transition on the SCL pin (see Figure 4).

– When the ST24LC21B (or the ST24FC21) is in

the I

C Bidirectional mode, the VCLK input

(pin 7) enables (or inhibits) the execution of

any write instruction: if VCLK = 1, write instruc-

tions are executed; if VCLK = 0, write instruc-

tions are not executed.

– When the ST24LW21 (or the ST24FW21) is in

the I

C Bidirectional mode, the Write Control

(WC on pin 3) input enables (or inhibits) the

execution of any write instruction: if WC = 1,

write instructions are executed;if WC = 0,

write instructions are not executed.

The ST24xy21 is compatible with the I

C standard,

two wire serial interface which uses a bidirectional

data bus and serial clock. The device carries a

built-in 4 bit, unique device identification code

(1010) named Device Select code corresponding

to the I

C bus definition.

The ST24xy21 behaves as a slave device in the

C protocol with all memory operations synchro-

nized by the serial clock SCL. Read and write

operations are initiated by a START condition gen-

erated by the bus master. The START condition is

followed by a stream of 7 bits (Device Select code

1010XXX), plus one read/write bit and terminated

by an acknowledge bit.

When data is written into the memory, the

ST24xy21 responds to the 8 bits received by as-

serting an acknowledge bit during the 9th bit time.

When data is read by the bus master, it must

acknowledges the receipt of the data bytes in the

same way. Data transfers are terminated with a

STOP condition (see READ and WRITE descrip-

tions in the following pages).

Power On Reset: V

lock out write protect

In order to prevent data corruption and inadvertent

write operations during power up, a Power On

Reset (POR) circuit is implemented. Until the V

voltage has reached the POR threshold value

(around 3V), the internal reset is active, all opera-

tions are disabled and the device will not respond

to any command. In the same way, when V

drops

down from the operating voltage to below the POR

threshold value, all operations are disabled and the

device will not respond to any command. A stable

must be applied before applying any logic

signal.

5/21

参数对比

与ST24LC21BM1相近的元器件有：ST24FW21M1、ST24FW21B1、ST24LC21BB1、ST24LW21B1、ST24LW21B6、ST24LW21M1、ST24LW21M6、ST24FC21M1、ST24FC21B1。描述及对比如下：

型号	ST24LC21BM1	ST24FW21M1	ST24FW21B1	ST24LC21BB1	ST24LW21B1	ST24LW21B6	ST24LW21M1	ST24LW21M6	ST24FC21M1	ST24FC21B1
描述	128X8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 0.150 INCH, PLASTIC, SO-8	128X8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 0.150 INCH, PLASTIC, SO-8	128X8 I2C/2-WIRE SERIAL EEPROM, PDIP8, 0.25 MM LEAD FRAME, SKINNY, PLASTIC, DIP-8	128X8 I2C/2-WIRE SERIAL EEPROM, PDIP8, 0.25 MM LEAD FRAME, SKINNY, PLASTIC, DIP-8	128X8 I2C/2-WIRE SERIAL EEPROM, PDIP8, 0.25 MM LEAD FRAME, SKINNY, PLASTIC, DIP-8	128X8 I2C/2-WIRE SERIAL EEPROM, PDIP8, 0.25 MM LEAD FRAME, SKINNY, PLASTIC, DIP-8	128X8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 0.150 INCH, PLASTIC, SO-8	128X8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 0.150 INCH, PLASTIC, SO-8	128X8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 0.150 INCH, PLASTIC, SO-8	128X8 I2C/2-WIRE SERIAL EEPROM, PDIP8, 0.25 MM LEAD FRAME, SKINNY, PLASTIC, DIP-8
是否Rohs认证	符合	符合	不符合	不符合	不符合	不符合	符合	符合	符合	不符合
厂商名称	ST(意法半导体)	ST(意法半导体)	ST(意法半导体)	ST(意法半导体)	ST(意法半导体)	ST(意法半导体)	ST(意法半导体)	ST(意法半导体)	ST(意法半导体)	ST(意法半导体)
零件包装代码	SOIC	SOIC	DIP	DIP	DIP	DIP	SOIC	SOIC	SOIC	DIP
包装说明	0.150 INCH, PLASTIC, SO-8	0.150 INCH, PLASTIC, SO-8	DIP, DIP8,.3	DIP, DIP8,.3	DIP, DIP8,.3	DIP, DIP8,.3	0.150 INCH, PLASTIC, SO-8	0.150 INCH, PLASTIC, SO-8	0.150 INCH, PLASTIC, SO-8	DIP, DIP8,.3
针数	8	8	8	8	8	8	8	8	8	8
Reach Compliance Code	compliant	compliant	not_compliant	not_compliant	not_compliant	not_compliant	compliant	compliant	compliant	not_compliant
ECCN代码	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
其他特性	40 YEAR DATA RETENTION	40 YEAR DATA RETENTION	40 YEAR DATA RETENTION	40 YEAR DATA RETENTION	40 YEAR DATA RETENTION	40 YEAR DATA RETENTION	40 YEAR DATA RETENTION	40 YEAR DATA RETENTION	40 YEAR DATA RETENTION	40 YEAR DATA RETENTION
最大时钟频率 (fCLK)	0.4 MHz	0.4 MHz	0.4 MHz	0.4 MHz	0.4 MHz	0.4 MHz	0.4 MHz	0.4 MHz	0.4 MHz	0.4 MHz
数据保留时间-最小值	40	40	40	40	40	40	40	40	40	40
耐久性	1000000 Write/Erase Cycles	1000000 Write/Erase Cycles	1000000 Write/Erase Cycles	1000000 Write/Erase Cycles	1000000 Write/Erase Cycles	1000000 Write/Erase Cycles	1000000 Write/Erase Cycles	1000000 Write/Erase Cycles	1000000 Write/Erase Cycles	1000000 Write/Erase Cycles
I2C控制字节	1010XXXR	1010XXXR	1010XXXR	1010XXXR	1010XXXR	1010XXXR	1010XXXR	1010XXXR	1010XXXR	1010XXXR
JESD-30 代码	R-PDSO-G8	R-PDSO-G8	R-PDIP-T8	R-PDIP-T8	R-PDIP-T8	R-PDIP-T8	R-PDSO-G8	R-PDSO-G8	R-PDSO-G8	R-PDIP-T8
JESD-609代码	e4	e4	e0	e0	e0	e0	e4	e4	e4	e0
长度	4.9 mm	4.9 mm	9.55 mm	9.55 mm	9.55 mm	9.55 mm	4.9 mm	4.9 mm	4.9 mm	9.55 mm
内存密度	1024 bit	1024 bit	1024 bit	1024 bit	1024 bit	1024 bit	1024 bit	1024 bit	1024 bit	1024 bit
内存集成电路类型	EEPROM	EEPROM	EEPROM	EEPROM	EEPROM	EEPROM	EEPROM	EEPROM	EEPROM	EEPROM
内存宽度	8	8	8	8	8	8	8	8	8	8
功能数量	1	1	1	1	1	1	1	1	1	1
端子数量	8	8	8	8	8	8	8	8	8	8
字数	128 words	128 words	128 words	128 words	128 words	128 words	128 words	128 words	128 words	128 words
字数代码	128	128	128	128	128	128	128	128	128	128
工作模式	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	70 °C	70 °C	70 °C	70 °C	70 °C	85 °C	70 °C	85 °C	70 °C	70 °C
组织	128X8	128X8	128X8	128X8	128X8	128X8	128X8	128X8	128X8	128X8
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	SOP	SOP	DIP	DIP	DIP	DIP	SOP	SOP	SOP	DIP
封装等效代码	SOP8,.25	SOP8,.25	DIP8,.3	DIP8,.3	DIP8,.3	DIP8,.3	SOP8,.25	SOP8,.25	SOP8,.25	DIP8,.3
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	SMALL OUTLINE	SMALL OUTLINE	IN-LINE	IN-LINE	IN-LINE	IN-LINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	IN-LINE
并行/串行	SERIAL	SERIAL	SERIAL	SERIAL	SERIAL	SERIAL	SERIAL	SERIAL	SERIAL	SERIAL
峰值回流温度（摄氏度）	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
电源	3.6/5.5 V	3.6/5.5 V	3.6/5.5 V	3.6/5.5 V	3.6/5.5 V	3.6/5.5 V	3.6/5.5 V	3.6/5.5 V	3.6/5.5 V	3.6/5.5 V
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	1.75 mm	1.75 mm	5.9 mm	5.9 mm	5.9 mm	5.9 mm	1.75 mm	1.75 mm	1.75 mm	5.9 mm
串行总线类型	I2C	I2C	I2C	I2C	I2C	I2C	I2C	I2C	I2C	I2C
最大待机电流	0.00003 A	0.00003 A	0.00003 A	0.00003 A	0.00003 A	0.00003 A	0.00003 A	0.00003 A	0.00003 A	0.00003 A
最大压摆率	0.002 mA	0.002 mA	0.002 mA	0.002 mA	0.002 mA	0.002 mA	0.002 mA	0.002 mA	0.002 mA	0.002 mA
最大供电电压 (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
最小供电电压 (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
标称供电电压 (Vsup)	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V
表面贴装	YES	YES	NO	NO	NO	NO	YES	YES	YES	NO
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL
端子面层	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Tin/Lead (Sn/Pb)
端子形式	GULL WING	GULL WING	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	GULL WING	GULL WING	GULL WING	THROUGH-HOLE
端子节距	1.27 mm	1.27 mm	2.54 mm	2.54 mm	2.54 mm	2.54 mm	1.27 mm	1.27 mm	1.27 mm	2.54 mm
端子位置	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
处于峰值回流温度下的最长时间	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
宽度	3.9 mm	3.9 mm	7.62 mm	7.62 mm	7.62 mm	7.62 mm	3.9 mm	3.9 mm	3.9 mm	7.62 mm
最长写入周期时间 (tWC)	10 ms	10 ms	10 ms	10 ms	10 ms	10 ms	10 ms	10 ms	10 ms	10 ms
写保护	-	HARDWARE	HARDWARE	-	HARDWARE	HARDWARE	HARDWARE	HARDWARE	-	-