ST93CS56
ST93CS57
2K (128 x 16) SERIAL MICROWIRE EEPROM
NOT FOR NEW DESIGN
1 MILLION ERASE/WRITE CYCLES, with
40 YEARS DATA RETENTION
SELF-TIMED PROGRAMMING CYCLE with
AUTO-ERASE
READY/BUSY SIGNAL DURING
PROGRAMMING
SINGLE SUPPLY VOLTAGE
– 3V to 5.5V for the ST93CS56
– 2.5V to 5.5V for the ST93CS57
USER DEFINED WRITE PROTECTED AREA
PAGE WRITE MODE (4 WORDS)
SEQUENTIAL READ OPERATION
5ms TYPICAL PROGRAMMING TIME
ST93CS56 and ST93CS57 are replaced by
the M93S56
8
1
PSDIP8 (B)
0.4mm Frame
8
1
SO8 (M)
150mil Width
Figure 1. Logic Diagram
DESCRIPTION
The ST93CS56 and ST93CS57 are 2K bit Electri-
cally Erasable Programmable Memory (EEPROM)
fabricated with SGS-THOMSON’s High Endurance
Single Polysilicon CMOS technology. The memory
is accessed through a serial input D and output Q.
The 2K bit memory is organized as 128 x 16 bit
words.The memory is accessed by a set of instruc-
tions which include Read, Write, Page Write, Write
All and instructions used to set the memory protec-
tion. A Read instruction loads the address of the
first word to be read into an internal address
pointer.
Table 1. Signal Names
S
D
Q
C
PRE
W
V
CC
V
SS
Chip Select Input
Serial Data Input
Serial Data Output
Serial Clock
Protect Enable
Write Enable
Supply Voltage
Ground
VCC
D
C
S
PRE
W
ST93CS56
ST93CS57
Q
VSS
AI00896B
June 1997
This is information on a product still in production bu t not recommended for new de signs.
1/16
ST93CS56, ST93CS57
Figure 2A. DIP Pin Connections
Figure 2B. SO Pin Connections
ST93CS56
ST93CS57
S
C
D
Q
1
2
3
4
8
7
6
5
AI00897B
ST93CS56
ST93CS57
VCC
PRE
W
VSS
S
C
D
Q
1
2
3
4
8
7
6
5
AI00898C
VCC
PRE
W
VSS
Table 2. Absolute Maximum Ratings
(1)
Symbol
T
A
T
STG
T
LEAD
V
IO
V
CC
V
ESD
Parameter
Ambient Operating Temperature
Storage Temperature
Lead Temperature, Soldering
(SO8 package)
(PSDIP8 package)
40 sec
10 sec
Value
–40 to 85
–65 to 150
215
260
–0.3 to V
CC
+0.5
–0.3 to 6.5
(2)
Unit
°C
°C
°C
V
V
V
V
Input or Output Voltages (Q = V
OH
or Hi-Z)
Supply Voltage
Electrostatic Discharge Voltage (Human Body model)
Electrostatic Discharge Voltage (Machine model)
(3)
3000
500
Notes:
1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings”
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other
relevant quality documents.
2. MIL-STD-883C, 3015.7 (100pF, 1500
Ω).
3. EIAJ IC-121 (Condition C) (200pF, 0
Ω).
DESCRIPTION
(cont’d)
The data is then clocked out serially. The address
pointer is automatically incremented after the data
is output and, if the Chip Select input (S) is held
High, the ST93CS56/57 can output a sequential
stream of data words. In this way, the memory can
be read as a data stream of 16 to 2048 bits, or
continuously as the address counter automatically
rolls over to 00 when the highest address is
reached. Within the time required by a program-
ming cycle (t
W
), up to 4 words may be written with
the help of the Page Write instruction; the whole
memory may also be erased, or set to a predeter-
mined pattern, by using the Write All instruction.
Within the memory, an user defined area may be
protected against further Write instructions. The
size of this area is defined by the content of a
Protect Register, located outside of the memory
array. As a final protection step, data may be per-
manently protected by programming a One Time
Programing bit (OTP bit) which locks the Protect
Register content.
Programming is internally self-timed (the external
clock signal on C input may be disconnected or left
running after the start of a Write cycle) and does
not require an erase cycle prior to the Write instruc-
tion. The Write instruction writes 16 bits at one time
into one of the 128 words, the Page Write instruc-
tion writes up to 4 words of 16 bits to sequential
locations, assuming in both cases that all ad-
dresses are outside the Write Protected area.
After the start of the programming cycle, a
Ready/Busy signal is available on the Data output
(Q) when the Chip Select (S) input pin is driven
High.
2/16
ST93CS56, ST93CS57
AC MEASUREMENT CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing
Reference Voltages
≤
20ns
0.2V
CC
to 0.8V
CC
0.3V
CC
to 0.7V
CC
Figure 3. AC Testing Input Output Waveforms
0.8VCC
0.7VCC
0.3VCC
AI00825
0.2VCC
Note that Output Hi-Z is defined as the point where data
is no longer driven.
Table 3. Capacitance
(1)
(T
A
= 25
°C,
f = 1 MHz )
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Test Condition
V
IN
= 0V
V
OUT
= 0V
Min
Max
5
5
Unit
pF
pF
Note:
1. Sampled only, not 100% tested.
Table 4. DC Characteristics
(T
A
= 0 to 70°C or –40 to 85°C; V
CC
= 3V to 5.5V for ST93CS56 and
V
CC
= 2.5V to 5.5V for ST93CS57)
Symbol
I
LI
I
LO
I
CC
Parameter
Input Leakage Current
Output Leakage Current
Supply Current (TTL Inputs)
Supply Current (CMOS Inputs)
I
CC1
Supply Current (Standby)
Input Low Voltage (ST93CS56,57)
V
IL
Input Low Voltage (ST93CS56)
Input Low Voltage (ST93CS57)
Input High Voltage (ST93CS56,57)
V
IH
Input High Voltage (ST93CS56)
Input High Voltage (ST93CS57)
V
OL
Output Low Voltage
Test Condition
0V
≤
V
IN
≤
V
CC
0V
≤
V
OUT
≤
V
CC
,
Q in Hi-Z
S = V
IH
, f = 1 MHz
S = V
IH
, f = 1 MHz
S = V
SS
, C = V
SS
4.5V
≤
V
CC
≤
5.5V
3V
≤
V
CC
≤
5.5V
2.5V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
3V
≤
V
CC
≤
5.5V
2.5V
≤
V
CC
≤
5.5V
I
OL
= 2.1mA
I
OL
= 10
µA
V
OH
Output High Voltage
I
OH
= –400µA
I
OH
= –10µA
2.4
V
CC
– 0.2
–0.1
–0.1
–0.1
2
0.8 V
CC
0.8 V
CC
Min
Max
±2.5
±2.5
3
2
50
0.8
0.2 V
CC
0.2 V
CC
V
CC
+ 1
V
CC
+ 1
V
CC
+ 1
0.4
0.2
Unit
µA
µA
mA
mA
µA
V
V
V
V
V
V
V
V
V
V
3/16
ST93CS56, ST93CS57
Table 5. AC Characteristics
(T
A
= 0 to 70°C or –40 to 85°C; V
CC
= 3V to 5.5V for ST93CS56 and
V
CC
= 2.5V to 5.5V for ST93CS57)
Symbol
t
PRVCH
t
WVCH
t
SHCH
t
DVCH
t
CHDX
t
CHQL
t
CHQV
t
CLPRX
t
SLWX
t
CLSL
t
SLSH
t
SHQV
t
SLQZ
t
CHCL
t
CLCH
t
W
f
C
Alt
t
PRES
t
PES
t
CSS
t
DIS
t
DIH
t
PD0
t
PD1
t
PREH
t
PEH
t
CSH
t
CS
t
SV
t
DF
t
SKH
t
SKL
t
WP
f
SK
Parameter
Protect Enable Valid to Clock High
Write Enable Valid to Clock High
Chip Select High to Clock High
Input Valid to Clock High
Clock High to Input Transition
Clock High to Output Low
Clock High to Output Valid
Clock Low to Protect Enable Transition
Chip Select Low to Write Enable Transition
Clock Low to Chip Select Transition
Chip Select Low to Chip Select High
Chip Select High to Output Valid
Chip Select Low to Output Hi-Z
Clock High to Clock Low
Clock Low to Clock High
Erase/Write Cycle time
Clock Frequency
0
Note 2
Note 2
250
250
10
1
Note 1
0
250
0
250
500
300
Test Condition
Min
50
50
50
100
100
500
500
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
MHz
Notes:
1. Chip Select must be brought low for a minimum of 250 ns (t
SLSH
) between consecutive instruction cycles.
2. The Clock frequency specification calls for a minimum clock period of 1
µs,
therefore the sum of the timings t
CHCL
+ t
CLCH
must be greater or equal to 1
µs.
For example, if t
CHCL
is 250 ns, then t
CLCH
must be at least 750 ns.
Figure 4. Synchronous Timing, Start and Op-Code Input
PRE
tPRVCH
W
tWVCH
C
tSHCH
S
tDVCH
D
START
OP CODE
tCHDX
OP CODE
tCLCH
tCHCL
OP CODE INPUT
START
AI00887
4/16
ST93CS56, ST93CS57
Figure 5. Synchronous Timing, Read or Write
C
tCLSL
S
tDVCH
D
An
tCHQL
Q15/Q7
tCHDX
A0
tSLQZ
Q0
tCHQV
tSLSH
Hi-Z
Q
ADDRESS INPUT
DATA OUTPUT
AI00820C
PRE
tCLPRX
W
tSLWX
C
tCLSL
S
tSLSH
tDVCH
D
An
tCHDX
A0/D0
tSHQV
Hi-Z
Q
BUSY
tW
ADDRESS/DATA INPUT
WRITE CYCLE
AI00888B
tSLQZ
READY
5/16
