DATA SHEET
2-CHANNEL HIGH DEFINITION AUDIO CODEC
Description
The STAC9200 is a high quality, 2-channel audio CODEC
compatible with the Intel High Definition (HD) Audio
Interface. The STAC9200 provides Stereo 24-Bit resolution
with sample rates up to 192 KHz. SPDIF I/O provides
connectivity to consumer electronic equipment. The
STAC9200 incorporates IDT's proprietary SD technology to
achieve an estimated DAC SNR in excess of 100dB. The
STAC9200 provides high quality, HD Audio capability to
notebook and cost sensitive desktop PC applications.
STAC9200
•
•
•
Mixer-less design
•
Low-latency Karaoke Mode Supported
Integrated Headphone Amplifiers
Stereo Microphone
•
•
•
•
•
•
•
•
•
Supports Stereo Microphone
Microphone Boost 0, 10, 20, 30, 40dB
Direct CDROM Recording Mixerless Design
S/PDIF In and Out
Universal Jacks
TM
Functionality for jack retasking
Adjustable VREF Out
Digital PC Beep to all outputs
+3.3 V, +4 V and +5 V analog power supply options
(The +4 V Analog voltage is supported by the +5 V version of
the STAC9200. Request +4 V configuration of the driver.)
Features
•
•
•
•
•
High performance
SD
technology
100dB DAC SNR
Intel HD Audio Interface
Two Channel DACs and ADCs with 24-bit
resolution
Sample rates up to 192 KHz
32-pad QFN (5mm x 5mm) and 48-pin LQFP
package options
IDT™
2-CHANNEL HIGH DEFINITION AUDIO CODEC
1
STAC9200
V 1.7 05/12
STAC9200
2-CHANNEL HIGH DEFINITION AUDIO CODEC
PC AUDIO
Table of Contents
1. DESCRIPTION ......................................................................................................................... 11
2. PERFORMANCE ..................................................................................................................... 12
2.1. Audio Fidelity ................................................................................................................................... 12
2.2. Electrical Specifications ................................................................................................................... 12
2.2.1. Absolute Maximum Ratings ............................................................................................... 12
2.2.2. Recommended Operation Conditions ............................................................................... 12
2.3. Power Consumption ........................................................................................................................ 13
2.3.1. Digital ................................................................................................................................. 13
2.3.2. Analog ............................................................................................................................... 13
2.4. STAC9200 5V Analog Performance Characteristics ....................................................................... 14
2.5. STAC9200 4V Analog Performance Characteristics ....................................................................... 16
2.6. STAC9200 3.3V Analog Performance Characteristics .................................................................... 18
3. EXTENDED FEATURE EXPLANATION ................................................................................. 20
3.1. SPDIF Input ..................................................................................................................................... 20
3.2. SPDIF Output .................................................................................................................................. 20
3.3. Universal JacksTM .......................................................................................................................... 20
3.4. Audio Jack Presence Detect ........................................................................................................... 20
4. BLOCK DIAGRAMS AND TYPICAL HOOKUPS .................................................................... 21
4.1. Functional Block Diagram ................................................................................................................ 21
4.2. STAC9200 Typical Connection Diagram for 48-pin LQFP .............................................................. 22
4.3. STAC9200 Split Independent Power Supply for 48-pin LQFP ........................................................ 22
4.4. STAC9200 Typical Connection Diagram for 32-pad QFN ............................................................... 22
4.5. STAC9200 Split Independent Power Supply for 32-pad QFN ......................................................... 22
5. WIDGET INFORMATION .........................................................................................................23
5.1. Widget Diagram ............................................................................................................................... 23
5.2. STAC9200 Widget List .................................................................................................................... 24
5.3. Root Node (NID = 0x00) .................................................................................................................. 25
5.3.1. Root PnpID ....................................................................................................................... 25
5.3.2. Root RevID ..................................................................................................................... 25
5.3.3. Root NodeInfo .................................................................................................................. 26
5.4. AFG Node (NID = 0x01) .................................................................................................................. 26
5.4.1. AFG Reset ........................................................................................................................ 26
5.4.2. AFG NodeInfo ................................................................................................................... 27
5.4.3. AFG Type ......................................................................................................................... 27
5.4.4. AFG GrpCap ..................................................................................................................... 27
5.4.5. AFG FrmtCap ................................................................................................................... 28
5.4.6. AFG StreamCap ............................................................................................................... 29
5.4.7. AFG PwrCap .................................................................................................................... 30
5.4.8. AFG GPIOCap .................................................................................................................. 30
5.4.9. AFG OutAmpCap ............................................................................................................. 31
5.4.10. AFG PwrState ................................................................................................................. 32
5.4.11. AFG UnsolResp .............................................................................................................. 32
5.4.12. AFG GPIO ...................................................................................................................... 33
5.4.13. AFG GPIOEn .................................................................................................................. 34
5.4.14. AFG GPIODir .................................................................................................................. 35
5.4.15. AFG GPIOWake ............................................................................................................. 35
5.4.16. AFG GPIOUnsolEn ......................................................................................................... 36
5.4.17. AFG GPIOSticky ............................................................................................................. 37
5.4.18. AFG SysID ...................................................................................................................... 38
5.5. DAC0Cnvtr Node (NID = 0x02) ....................................................................................................... 39
5.5.1. DAC0Cnvtr Frmt ............................................................................................................... 39
5.5.2. DAC0Cnvtr WCap ............................................................................................................ 40
5.5.3. DAC0Cnvtr PwrState ......................................................................................................... 41
IDT™
2-CHANNEL HIGH DEFINITION AUDIO CODEC
2
STAC9200
V 1.7 05/12
STAC9200
2-CHANNEL HIGH DEFINITION AUDIO CODEC
PC AUDIO
5.5.4. DAC0Cnvtr Stream ........................................................................................................... 42
5.6. ADC0Cnvtr Node (NID = 0x03) ...................................................................................................... 42
5.6.1. ADC0Cnvtr Frmt ............................................................................................................... 42
5.6.2. ADC0Cnvtr WCap ............................................................................................................ 43
5.6.3. ADC0Cnvtr ConnLen ........................................................................................................ 44
5.6.4. ADC0Cnvtr ConnLst ......................................................................................................... 45
5.6.5. ADC0Cnvtr ProcState ....................................................................................................... 45
5.6.6. ADC0Cnvtr PwrState ........................................................................................................ 46
5.6.7. ADC0Cnvtr Stream ........................................................................................................... 47
5.7. SPDIFinCnvtr Node (NID = 0x04) ................................................................................................... 47
5.7.1. SPDIFinCnvtr Frmt ........................................................................................................... 47
5.7.2. SPDIFinCnvtr WCap ......................................................................................................... 48
5.7.3. SPDIFinCnvtr FrmtCap ..................................................................................................... 49
5.7.4. SPDIFinCnvtr StreamCap ................................................................................................ 50
5.7.5. SPDIFinCnvtr ConnLen .................................................................................................... 51
5.7.6. SPDIFinCnvtr ConnLst ..................................................................................................... 51
5.7.7. SPDIFinCnvtr Stream ....................................................................................................... 52
5.7.8. SPDIFinCnvtr DigCtl ......................................................................................................... 52
5.8. SPDIFoutCnvtr Node (NID = 0x05) ................................................................................................. 53
5.8.1. SPDIFoutCnvtr Frmt ......................................................................................................... 53
5.8.2. SPDIFoutCnvtr WCap ...................................................................................................... 54
5.8.3. SPDIFoutCnvtr FrmtCap .................................................................................................. 55
5.8.4. SPDIFoutCnvtr StreamCap .............................................................................................. 56
5.8.5. SPDIFoutCnvtr Stream ..................................................................................................... 57
5.8.6. SPDIFoutCnvtr DigCtl ....................................................................................................... 57
5.9. DAC0Mux Node (NID = 0x07) ........................................................................................................ 58
5.9.1. DAC0Mux WCap .............................................................................................................. 58
5.9.2. DAC0Mux ConnLen .......................................................................................................... 59
5.9.3. DAC0Mux ConnSel .......................................................................................................... 60
5.9.4. DAC0Mux ConnLst ........................................................................................................... 60
5.9.5. DAC0Mux LR .................................................................................................................... 60
5.10. DigInPin Node (NID = 0x08) .......................................................................................................... 61
5.10.1. DigInPin WCap ............................................................................................................... 61
5.10.2. DigInPin Cap .................................................................................................................. 62
5.10.3. DigInPin PwrState .......................................................................................................... 63
5.10.4. DigInPin Ctl ...................................................................................................................... 63
5.10.5. DigInPin UnsolResp ....................................................................................................... 64
5.10.6. DigInPin Sense ............................................................................................................... 64
5.10.7. DigInPin EAPD ............................................................................................................... 65
5.10.8. DigInPin Config ............................................................................................................... 65
5.11. DigOutPin Node (NID = 0x09) ....................................................................................................... 66
5.11.1. DigOutPin WCap ............................................................................................................ 66
5.11.2. DigOutPin Cap ................................................................................................................ 67
5.11.3. DigOutPin ConnLen ........................................................................................................ 68
5.11.4. DigOutPin ConnSel ........................................................................................................ 69
5.11.5. DigOutPin ConnLst ......................................................................................................... 69
5.11.6. DigOutPin Ctl .................................................................................................................. 69
5.11.7. DigOutPin Config ............................................................................................................ 70
5.12. ADC0Mux Node (NID = 0x0A) ....................................................................................................... 71
5.12.1. ADC0Mux VolRight ......................................................................................................... 71
5.12.2. ADC0Mux VolLeft ........................................................................................................... 71
5.12.3. ADC0Mux WCap ............................................................................................................ 72
5.12.4. ADC0Mux OutAmpCap .................................................................................................. 73
5.12.5. ADC0Mux ConnLen ........................................................................................................ 73
5.12.6. ADC0Mux ConnLst ......................................................................................................... 74
IDT™
2-CHANNEL HIGH DEFINITION AUDIO CODEC
3
STAC9200
V 1.7 05/12
STAC9200
2-CHANNEL HIGH DEFINITION AUDIO CODEC
PC AUDIO
5.12.7. ADC0Mux LR .................................................................................................................. 74
5.13. MasterVol Node (NID = 0x0B) ....................................................................................................... 75
5.13.1. MasterVol Right .............................................................................................................. 75
5.13.2. MasterVol Left ................................................................................................................ 75
5.13.3. MasterVol WCap ............................................................................................................ 76
5.13.4. MasterVol ConnLen ........................................................................................................ 77
5.13.5. MasterVol ConnLst ......................................................................................................... 77
5.14. InPortMux Node (NID = 0x0C) ...................................................................................................... 78
5.14.1. InPortMux VolRight ......................................................................................................... 78
5.14.2. InPortMux VolLeft ........................................................................................................... 78
5.14.3. InPortMux WCap ............................................................................................................ 79
5.14.4. InPortMux ConnLen ........................................................................................................ 80
5.14.5. InPortMux AmpCap ........................................................................................................ 80
5.14.6. InPortMux ConnSel ........................................................................................................ 81
5.14.7. InPortMux ConnLst0 ....................................................................................................... 81
5.14.8. InPortMux ConnLst4 ....................................................................................................... 81
5.15. PortAPin Node (NID = 0x0D) ......................................................................................................... 82
5.15.1. PortAPin WCap .............................................................................................................. 82
5.15.2. PortAPin Cap .................................................................................................................. 83
5.15.3. PortAPin ConnLen .......................................................................................................... 84
5.15.4. PortAPin ConnLst ........................................................................................................... 84
5.15.5. PortAPin Ctl .................................................................................................................... 84
5.15.6. PortAPin UnsolResp ....................................................................................................... 85
5.15.7. PortAPin Sense .............................................................................................................. 86
5.15.8. PortAPin Config .............................................................................................................. 86
5.16. PortDPin Node (NID = 0x0E) ......................................................................................................... 87
5.16.1. PortDPin WCap .............................................................................................................. 87
5.16.2. PortDPin Cap .................................................................................................................. 88
5.16.3. PortDPin ConnLen .......................................................................................................... 89
5.16.4. PortDPin ConnLst ........................................................................................................... 89
5.16.5. PortDPin Ctl .................................................................................................................... 90
5.16.6. PortDPin UnsolResp ....................................................................................................... 90
5.16.7. PortDPin Sense .............................................................................................................. 91
5.16.8. PortDPin Config .............................................................................................................. 92
5.17. PortCPin Node (NID = 0x0F) ......................................................................................................... 92
5.17.1. PortCPin WCap .............................................................................................................. 92
5.17.2. PortCPin Cap .................................................................................................................. 93
5.17.3. PortCPin ConnLen .......................................................................................................... 94
5.17.4. PortCPin ConnLst ........................................................................................................... 95
5.17.5. PortCPin Ctl .................................................................................................................... 95
5.17.6. PortCPin UnsolResp ....................................................................................................... 96
5.17.7. PortCPin Sense .............................................................................................................. 96
5.17.8. PortCPin Config .............................................................................................................. 97
5.18. PortBPin Node (NID = 0x10) ......................................................................................................... 98
5.18.1. PortBPin WCap .............................................................................................................. 98
5.18.2. PortBPin Cap .................................................................................................................. 99
5.18.3. PortBPin ConnLen ........................................................................................................ 100
5.18.4. PortBPin ConnLst ......................................................................................................... 100
5.18.5. PortBPin Ctl .................................................................................................................. 100
5.18.6. PortBPin UnsolResp ..................................................................................................... 101
5.18.7. PortBPin Sense ............................................................................................................ 102
5.18.8. PortBPin Config ............................................................................................................ 102
5.19. MonoOutPin Node (NID = 0x11) ................................................................................................. 103
5.19.1. MonoOutPin Vol ........................................................................................................... 103
5.19.2. MonoOutPin WCap ....................................................................................................... 104
IDT™
2-CHANNEL HIGH DEFINITION AUDIO CODEC
4
STAC9200
V 1.7 05/12
STAC9200
2-CHANNEL HIGH DEFINITION AUDIO CODEC
PC AUDIO
5.19.3. MonoOutPin Cap .......................................................................................................... 105
5.19.4. MonoOutPin ConnLen .................................................................................................. 105
5.19.5. MonoOutPin ConnLst ................................................................................................... 106
5.19.6. MonoOutPin Ctl ............................................................................................................ 106
5.19.7. MonoOutPin Config ...................................................................................................... 107
5.20. CDPin Node (NID = 0x12) ........................................................................................................... 108
5.20.1. CDPin WCap ................................................................................................................ 108
5.20.2. CDPin Cap .................................................................................................................... 109
5.20.3. CDPin Ctl ...................................................................................................................... 110
5.20.4. CDPin Config ................................................................................................................ 110
5.21. MonoOutMix Node (NID = 0x13) ................................................................................................. 111
5.21.1. MonoOutMix WCap ...................................................................................................... 111
5.21.2. MonoOutMix ConnLen .................................................................................................. 112
5.21.3. MonoOutMix ConnLst ................................................................................................... 112
5.22. PCBeep Node (NID = 0x14) ........................................................................................................ 113
5.22.1. PCBeep Vol .................................................................................................................. 113
5.22.2. PCBeep WCap ............................................................................................................. 113
5.22.3. PCBeep OutAmpCap ................................................................................................... 114
5.22.4. PCBeep Gen ................................................................................................................ 115
6. ORDERING INFORMATION .................................................................................................. 116
6.1. STAC9200 Family Options and Part Order Numbers .................................................................... 116
7. PIN INFORMATION ............................................................................................................... 117
7.1. Pin Out .......................................................................................................................................... 117
7.2. Pin Table for 48-pin LQFP and 32-pad QFN Packages ............................................................... 118
8. PACKAGE DRAWINGS ......................................................................................................... 120
8.1. 32-pin QFN .................................................................................................................................... 120
8.2. 48-Pin LQFP .................................................................................................................................. 121
9. SOLDER REFLOW PROFILE ............................................................................................... 122
9.1. Standard Reflow Profile Data ........................................................................................................ 122
9.2. Pb Free Process - Package Classification Reflow Temperatures ................................................. 123
10. REVISION HISTORY ........................................................................................................... 124
List of Figures
Figure 1. Functional Block Diagram ............................................................................................................... 21
Figure 2. Widget Diagram .............................................................................................................................. 23
Figure 3. 32-Pad QFN Package Outline and Package Dimensions ............................................................ 120
Figure 4. 48-Pin LQFP Package Outline and Package Dimensions ........................................................... 121
Figure 5. Solder Reflow Profile ................................................................................................................... 122
List of Tables
Table 1. Digital Power Consumption ............................................................................................................. 13
Table 2. Analog Power Consumption ............................................................................................................ 13
Table 3. High Definition Audio Widget ........................................................................................................... 24
Table 4. Root PnpID Command Verb Format ................................................................................................ 25
Table 5. Root PnpID Command Response Format ....................................................................................... 25
Table 6. Root RevID Command Verb Format ................................................................................................ 25
Table 7. Root RevID Command Response Format ....................................................................................... 25
IDT™
2-CHANNEL HIGH DEFINITION AUDIO CODEC
5
STAC9200
V 1.7 05/12