首页 > 器件类别 >

STDRIVE101

Triple half-bridge gate driver

厂商名称:ST(意法半导体)

厂商官网:http://www.st.com/

下载文档
STDRIVE101 在线购买

供应商:

器件:STDRIVE101

价格:-

最低购买:-

库存:点击查看

点击购买

参考设计
展开全部 ↓
文档预览
STDRIVE101
Datasheet
Triple half-bridge gate driver
Features
Operating voltage from 5.5 to 75 V
600 mA sink/source current capability
3.3 V and 5 V control logic
Two input strategies:
ENx/INx with adjustable deadtime generation
INHx/INLx with interlocking
Matched propagation delay for all channels
Very short propagation delay: 40 ns
Integrated bootstrap diodes
12 V LDO linear regulator (50 mA max.)
Embedded V
DS
monitor for each external MOSFET
Overcurrent comparator
UVLO and thermal shutdown protection
Standby mode for low current consumption operation
Application
Home automation and appliances
e-bikes
Power tools
Fans and pumps
Industrial automation
Textile machines
Gaming and consoles
Product status link
STDRIVE101
Product label
Description
The STDRIVE101 is a low voltage gate driver suitable for driving three-phase
brushless motors.
It is a single-chip with three half-bridge gate drivers for N-channel power MOSFETs.
Each driver has a current capability of 600 mA (sink/source). It integrates a low drop
linear regulator generating the supply voltage for both low-side and high-side gate
drivers through a bootstrap circuitry.
The device provides Under Voltage Lock Out (UVLO) on both the low-side and high-
side sections, preventing the power switches from operating in low efficiency or
dangerous conditions.
The control logic integrated into the STDRIVE101 allows two input strategies (high-
side and low-side or enable and PWM driving signals). The driving method is
selected according to DT/MODE pin. In both cases, prevention from cross conduction
is ensured by interlocking or internally generated deadtime.
The STDRIVE101 also features a V
DS
monitoring protection for each external
MOSFET, thermal shutdown and can be put in the standby mode to reduce the
power consumption.
The device is available in a VFQFPN 4x4 24 leads package option.
DS13472
-
Rev 1
-
October 2020
For further information contact your local STMicroelectronics sales office.
www.st.com
STDRIVE101
Block diagram
1
Block diagram
Figure 1.
STDRIVE101 block diagram
12V
VM
REG12
+
VS
12 V
LDO Reg
STBY
+
VCC
VBOOT
BOOT1
GHS1
HS
+
-
+
-
+
OUT1
VCC
GLS1
LS
VDSth
BOOT2
GHS2
OUT2
GLS2
BOOT3
GHS3
Half-bridge 2
Half-bridge 1
VCC
VSCREF
SCREF
DT/MODE
IN3/INH3
IN2/INH2
IN1/INH1
VDSth
EN3/INL3
EN2/INL2
EN1/INL1
VDD
nFAULT
Decoding logic
and dead-time
M
OUT3
GLS3
Half-bridge 3
CP
+
-
VREF
DS13472
-
Rev 1
GND
page 2/32
STDRIVE101
Electrical data
2
2.1
Electrical data
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in
Table 1
may cause permanent damage to the device.
Exposure to maximum rating conditions for extended periods may affect device reliability.
Table 1.
Absolute maximum ratings
Symbol
V
S
dV
S
/dt
V
REG12
V
OUTx
V
BOOTx
V
BOx
V
GHSx
V
GLSx
dV
OUT
/dt
V
IN
V
CP
V
DT/MODE
V
SCREF
V
FAULT
I
FAULT
T
stg
T
J
Parameter
Supply voltage
Supply voltage slew rate
Gate driving supply voltage
OUTx pin voltage
Bootstrap pin voltage
High-side driver supply voltage
High-side gates voltage
Low-side gates voltage
Output slew rate
Logic input voltage
Overcurrent comparator inputs
voltage
Deadtime input voltage
V
DS
monitoring protection
reference voltage
nFAULT output voltage
nFAULT output sink current
Storage temperature
Junction temperature
V
BOOTx
- V
OUTx
REG12 shorted to VS
Test Condition
Value
-0.3 to 78
± 10
-0.3 to 20
-2 to V
S
+ 2
-0.3 to 98
-0.3 to 20
V
OUT
-0.3 to V
BOOT
+0.3
-0.3 to V
REG12
+0.3
± 10
-0.3 to 5.5
-2 to 5.5
-0.3 to 3.6
-0.3 to 3.6
-0.3 to 5.5
Up to 8
-55 to 150
-40 to 150
Unit
V
V/µs
V
V
V
V
V
V
V/ns
V
V
V
V
V
mA
°C
°C
DS13472
-
Rev 1
page 3/32
STDRIVE101
Recommended operating conditions
2.2
Recommended operating conditions
Table 2.
Recommended operating conditions
Symbol
V
S
V
REG12
V
BOOTx
I
REG12
C
REG12
R
DT
V
IN
V
CP
V
SCREF
V
FAULT
T
amb
Parameter
Supply voltage
12 V linear regulator output and
gate driving supply voltage
Bootstrap pin voltage
12 V linear regulator total current
consumption
(2)
12 V linear regulator output
capacitance
Deadtime resistor
Logic input voltage
Overcurrent comparator input
voltage
V
DS
monitoring protection
reference voltage
(4)
nFAULT output voltage
Operative ambient temperature
Protection enabled
Protection disabled
ENx/INx mode
INHx/INLx mode
0
-1
0.2
2.9
0
-40
Internal (gate drivers) and external
consumption
4.7
50
Short to ground
5
(3)
1
2.5
3.3
5
125
(5)
250
V
S
≥ 15 V
VS shorted to REG12
5.5
(1)
Test Condition
Min.
5.5
(1)
12
15
89
50
Typ.
Max.
75
Unit
V
V
V
V
mA
µF
kΩ
V
V
V
V
V
°C
1. Actual operative range can be limited by UVLO protections
2. Actual linear regulator current consumption can be limited by power dissipation
3. All digital inputs are 3.3 V TTL/CMOS thresholds compliant and 5 V tolerant. They can be biased within the respective AMR
whatever the supply condition of the device (supplied, floating or shorted to ground) without causing damage to the device.
4. SCREF pin structure does not allow a bias without VS supply voltage
5. Actual operative range is limited by thermal shutdown
Important:
It is mandatory to use a VS voltage equal or greater than power stage voltage (VM in
Figure 1).
If not, the device is
damaged.
DS13472
-
Rev 1
page 4/32
STDRIVE101
Thermal data
2.3
Thermal data
Table 3.
Thermal data
Symbol
R
thJA
R
thJCtop
R
thJCbot
R
thJB
Ψ
JT
Ψ
JB
Parameter
Junction-to-ambient thermal
resistance
Junction-to-case thermal
resistance (top side)
Junction-to-case thermal
resistance (bottom side)
Junction-to-board thermal
resistance
Junction-to-top
characterization parameter
Junction-to-board
characterization parameter
Conditions
Natural convection, according to JESD51-2a
(1)
Cold plate on top, according to JESD51-12
(1)
Cold plate on exposed pad, according to JESD51-12
(1)
According to JESD51-8
(1)
According to JESD51-2a
(1)
According to JESD51-2a
(1)
Value
94.5
28.4
1.47
14.4
0.6
14.2
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
1. Simulated on a 21.2x21.2 mm board, 2s2p 1 Oz copper and four 300 µm vias below exposed pad.
2.4
Electrical sensitivity characteristics
Table 4.
ESD protection ratings
Symbol
HBM
CDM
Parameter
Human Body Model
Charge Device Model
Test Condition
Conforming to ANSI/ESDA/JEDEC JS-001-2017
Conforming to ANSI/ESDA/JEDEC JS-002-2014
Class
H2
C2B
Value
2
750
Unit
kV
V
DS13472
-
Rev 1
page 5/32
查看更多>
热门器件
热门资源推荐
器件捷径:
00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W
需要登录后才可以下载。
登录取消