STK14CA8
128Kx8 AutoStore™ nvSRAM
Features
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Description
The Cypress STK14CA8 is a 1 Mb fast static RAM with a nonvol-
atile QuantumTrap™ storage element included with each
memory cell. This SRAM provides fast access and cycle times,
ease of use, and unlimited read and write endurance of a normal
SRAM.
Data transfers automatically to the nonvolatile storage cells
when power loss is detected (the STORE operation). On power
up, data is automatically restored to the SRAM (the RECALL
operation). Both STORE and RECALL operations are also
available under software control.
The Cypress nvSRAM is the first monolithic nonvolatile memory
to offer unlimited writes and reads. It is the highest performing
and most reliable nonvolatile memory available.
25, 35, 45 ns Read Access and Read/Write Cycle Time
Unlimited Read/Write Endurance
Automatic Nonvolatile STORE on Power Loss
Nonvolatile STORE Under Hardware or Software Control
Automatic RECALL to SRAM on Power Up
Unlimited RECALL Cycles
200K STORE Cycles
20-Year Nonvolatile Data Retention
Single 3.0V + 20%, -10% Operation
Commercial and Industrial Temperatures
Small Footprint SOIC and SSOP Packages (RoHS Compliant)
Logic Block Diagram
V
CC
A
5
A
6
A
7
A
8
A
9
A
12
A
13
A
14
A
15
A
16
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
Quantum Trap
1024 X 1024
ROW DECODER
STORE
STATIC RAM
ARRAY
1024 X 1024
RECALL
STORE/
RECALL
CONTROL
V
CAP
POWER
CONTROL
HSB
SOFTWARE
DETECT
INPUT BUFFERS
COLUMN I/O
COLUMN DEC
A
15
– A
0
A
0
A
1
A
2
A
3
A
4
A
10
A
11
G
E
W
Cypress Semiconductor Corporation
Document Number: 001-51592 Rev. **
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised March 04, 2009
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STK14CA8
Pinouts
Figure 1. 48-Pin SSOP
V
CAP
A
16
A
14
A
12
A
7
A
6
A
5
NC
A
4
NC
NC
NC
V
SS
NC
NC
DQ
0
A
3
A
2
A
1
A
0
DQ
1
DQ
2
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
V
CC
A
15
HSB
W
A
13
A
8
A
9
NC
A
11
NC
NC
NC
V
SS
NC
NC
DQ
6
G
A
10
E
DQ
7
DQ
5
DQ
4
DQ
3
V
CC
Figure 2. 32-Pin SOIC
V
CAP
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A
15
HSB
W
A
13
A
8
A
9
A
11
G
A
10
E
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
Figure 3. Relative PCB Area Usage
[1]
Pin Descriptions
Pin Name
A
16
-A
0
DQ
7
-DQ
0
E
W
G
V
CC
HSB
I/O
Input
I/O
Input
Input
Input
Power Supply
I/O
Description
Address: The 17 address inputs select one of 131,072 bytes in the nvSRAM array.
Data: Bi-directional 8-bit data bus for accessing the nvSRAM.
Chip Enable: The active low E input selects the device.
Write Enable: The active low W allows to write the data on the DQ pins to the address location
latched by the falling edge of E.
Output Enable: The active low G input enables the data output buffers during read cycles.
De-asserting G high causes the DQ pins to tri-state.
Power: 3.0V, +20%, -10%.
Hardware Store Busy: When low this output indicates a Store is in progress. When pulled low
external to the chip, it initiates a nonvolatile STORE operation. A weak pull up resistor keeps this
pin high if not connected. (Connection is optional).
AutoStore™ Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM to
nonvolatile storage elements.
Ground.
Unlabeled pins have no internal connections.
V
CAP
V
SS
NC
Power Supply
Power Supply
No Connect
Note
1. See
Package Diagrams
on page 15 for detailed package size specifications.
Document Number: 001-51592 Rev. **
Page 2 of 16
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STK14CA8
Absolute Maximum Ratings
Voltage on Input Relative to Ground.................–0.5V to 4.1V
Voltage on Input Relative to V
SS
...........–0.5V to (V
CC
+ 0.5V)
Voltage on DQ
0-7
or HSB ......................–0.5V to (V
CC
+ 0.5V)
Temperature under Bias ............................... –55°C to 125°C
Junction Temperature ................................... –55°C to 140°C
Storage Temperature .................................... –65°C to 150°C
Power Dissipation............................................................. 1W
DC Output Current (1 output at a time, 1s duration).... 15 mA
NF (SOP-32) PACKAGE THERMAL CHARACTERISTICS
θ
jc
5.4 C/W;
θ
ja
44.3 [0fpm], 37.9 [200fpm], 35.1 C/W [500fpm].
RF (SSOP-48) PACKAGE THERMAL CHARACTERISTICS
θ
jc
6.2 C/W;
θ
ja
51.1 [0fpm], 44.7 [200fpm], 41.8 C/W [500fpm].
Note:
Stresses greater than those listed under
Absolute
Maximum Ratings
may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device
at conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
DC Characteristics
(V
CC
= 2.7V to 3.6V)
Symbol
I
CC1
Parameter
Average V
CC
Current
Commercial
Min
Max
65
55
50
Industrial
Min
Max
70
60
55
Units
Notes
mA t
AVAV
= 25 ns
mA t
AVAV
= 35 ns
mA t
AVAV
= 45 ns
Dependent on output loading and cycle
rate. Values obtained without output loads.
mA All Inputs Don’t Care, V
CC
= max
Average current for duration of STORE
cycle (t
STORE
)
I
CC2
Average V
CC
Current during
STORE
Average V
CC
Current at t
AVAV
=
200 ns
3V, 25°C, Typical
Average V
CAP
Current during
AutoStore Cycle
V
CC
Standby Current
(Standby, Stable CMOS Levels)
3
3
I
CC3
10
10
mA W
≥
(V
CC
– 0.2V)
All Other Inputs Cycling at CMOS Levels
Dependent on output loading and cycle
rate. Values obtained without output loads.
I
CC4
3
3
I
SB
3
3
mA E
≥ (
V
CC
-0.2V)
All Others V
IN
≤
0.2V or
≥
(V
CC
-0.2V)
Standby current level after nonvolatile
cycle complete
μA
μA
V
V
V
V
V
CC
= max
V
IN
= V
SS
to V
CC
V
CC
= max
V
IN
= V
SS
to V
CC
, E or G
All Inputs
All Inputs
I
OUT
= – 2 mA
I
OUT
= 4 mA
3.3V + 0.3V
mA All Inputs Don’t Care
Average current for duration of STORE
cycle (t
STORE
)
I
ILK
I
OLK
V
IH
V
IL
V
OH
V
OL
T
A
V
CC
V
CAP
NV
C
DATA
R
Note
Input Leakage Current
Off-State Output Leakage
Current
Input Logic “1” Voltage
Input Logic “0” Voltage
Output Logic “1” Voltage
Output Logic “0” Voltage
Operating Temperature
Operating Voltage
Storage Capacitance
Nonvolatile STORE operations
Data Retention
0
2.7
17
200
20
2.0
V
SS
–0.5
2.4
±1
±1
V
CC
+0.3
0.8
0.4
70
3.6
120
–40
2.7
17
200
20
2.0
V
SS
–0.5
2.4
±1
±1
V
CC
+0.3
0.8
0.4
85
3.6
120
≥
V
IH
°
C
V
μF
K
Years At 55
°
C
Between V
CAP
pin and V
SS
, 5V rated.
The HSB pin has I
OUT
=-10 uA for V
OH
of 2.4 V, this parameter is characterized but not tested.
Page 3 of 16
Document Number: 001-51592 Rev. **
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STK14CA8
AC Test Conditions
Input Pulse Levels ....................................................0V to 3V
Input Rise and Fall Times
................................................. ≤
5 ns
Input and Output Timing Reference Levels .................... 1.5V
Output Load..................................See
Figure 4
and
Figure 5
Capacitance
(T
A
= 25°C, f = 1.0 MHz)
Symbol
C
IN
C
OUT
Parameter
[2]
Input Capacitance
Output Capacitance
Max Units
7
7
pF
pF
Conditions
Δ
V = 0 to 3V
Δ
V = 0 to 3V
Figure 4. AC Output Loading
3.0V
577 Ohms
OUTPUT
789 Ohms
30 pF
INCLUDING
SCOPE AND
FIXTURE
Figure 5. AC Output Loading for Tristate Specifications
(t
HZ
, t
LZ
, t
WLQZ
, t
WHQZ
, t
GLQX
, t
GHQZ
)
3.0V
577 Ohms
OUTPUT
789 Ohms
5 pF
INCLUDING
SCOPE AND
FIXTURE
Note
2. These parameters are guaranteed but not tested.
Document Number: 001-51592 Rev. **
Page 4 of 16
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STK14CA8
SRAM READ Cycles #1 and #2
NO.
#1
1
2
3
4
5
6
Symbols
Parameter
#2
t
ELQV
t
AVAV[3]
t
AVQV[4]
t
AXQX[4]
t
ELEH[3]
t
AVQV[4]
t
GLQV
t
AXQX[4]
t
ELQX
t
EHQZ[5]
t
GLQX
t
GHQZ[5]
t
ELICCH[2]
t
EHICCL[2]
Alt.
t
ACS
t
RC
t
AA
t
OE
t
OH
t
LZ
t
HZ
t
OLZ
t
OHZ
t
PA
t
PS
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Address Change or Chip Enable to
Output Active
Address Change or Chip Disable to
Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
STK14CA8-25 STK14CA8-35 STK14CA8-45
Min
25
25
12
3
3
10
0
10
0
25
0
35
0
13
0
45
3
3
13
0
15
Max
25
35
35
15
3
3
15
Min
Max
35
45
45
20
Min
Max
45
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
8
9
10
11
Figure 6. SRAM READ Cycle #1: Address Controlled
[3, 4, 6]
2
t
AVAV
ADDRESS
5
t
AXQX
DQ (DATA OUT)
DATA VALID
3
t
AVQV
Figure 7. SRAM READ Cycle #2: E and G Controlled
[3, 6]
2
1
6
29
11
7
3
9
4
8
10
Notes
3. W must be high during SRAM READ cycles.
4. Device is continuously selected with E and G both low
5. Measured
±
200mV from steady state output voltage.
6. HSB must remain high during READ and WRITE cycles
Document Number: 001-51592 Rev. **
Page 5 of 16
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