STK14EC16
Preliminary
FEATURES
• 15, 25, 45 ns Read Access and R/W Cycle Time
• Unlimited Read/Write Endurance
• Automatic Non-volatile STORE on Power Loss
• Non-Volatile STORE Under Hardware or Software
Control
• Automatic RECALL to SRAM on Power Up
• Unlimited RECALL Cycles
• 200K STORE Endurance
• 20-Year Non-volatile Data Retention
• Single 3.0V +20%, -10% Operation
• Commercial, Industrial Temperatures
• 44-pin or 54-pin 400-mil TSOPII Packages (RoHS-
Compliant)
• 48-ball Fine Pitch Ball Grid Array (FBGA)
256Kx16 AutoStore nvSRAM
DESCRIPTION
The Simtek STK14EC16 is a 4MB fast static RAM
with a non-volatile Quantum Trap storage element
included with each memory cell.
The SRAM provides the fast access & cycle times,
ease of use and unlimited read & write endurance of
a normal SRAM.
Data transfers automatically to the non-volatile stor-
age cells when power loss is detected (the
STORE
operation). On power up, data is automatically
restored to the SRAM (the
RECALL
operation). Both
STORE and RECALL operations are also available
under software control.
The Simtek nvSRAM is the highest performance,
most reliable non-volatile memory available.
BLOCK DIAGRAM
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
17
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
DQ
8
DQ
9
DQ
10
DQ
11
DQ
12
DQ
13
DQ
14
DQ
15
Row Decoder
EEPROM Array
2048 x 2048
STORE
SRAM
Array
2048 x 2048
Store/
Recall
Control
RECALL
Power
Control
V
CC
V
CAP
HSB
Input Buffers
Software
Detect
A0 - A17
Column I/O
Column Decoder
G
W
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
E
UB
Pachuco Boys
LB
This is a product in development that has fixed tar-
get specifications that are subject to change pend-
ing characterization results.
SIMTEK Confidential & Proprietary
1
Document Control #ML0061 Rev 1.1
Jan, 2008
STK14EC16
Truth Table for SRAM Operations
Operating Mode
Standby/not selected
E
H
L
Internal Read
L
Lower Byte Read
Upper Byte Read
Word Read
Lower Byte Write
Upper Byte Write
Word Write
L
L
L
L
L
L
H
H
H
H
H
H
H
X
H
H
H
L
L
L
X
L
L
L
X
X
X
H
L
H
L
L
H
L
H
H
L
L
H
L
L
High-Z
Data Outputs Low-Z
High-Z
Data Outputs Low-Z
Data Inputs High-Z
High-Z
Data Inputs High-Z
HSB
H
H
W
X
H
G
X
H
LB
X
X
UB
X
X
DQ0-DQ7
High-Z
High-Z
Preliminary
DQ8-DQ15
High-Z
High-Z
High-Z
High-Z
Data Outputs Low-Z
Data Outputs Low-Z
High-Z
Data Inputs High-Z
Data Inputs High-Z
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Simtek Confidential
Preliminary
STK14EC16
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
17
A
16
A
15
G
UB
LB
DQ
15
DQ
14
DQ
13
DQ
12
V
SS
V
CC
DQ
11
DQ
10
DQ
9
DQ
8
V
CAP
A
14
A
13
A
12
A
11
A
10
NC
NC
A
0
A
1
A
2
A
3
A
4
E
DQ
0
DQ
1
DQ
2
DQ
3
V
CC
V
SS
DQ
4
DQ
5
DQ
6
DQ
7
W
A
5
A
6
A
7
A
8
A
9
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
1
HSB
NC
A
17
A
16
A
15
G
UB
LB
DQ
15
DQ
14
DQ
13
DQ
12
V
SS
V
CC
DQ
11
DQ
10
DQ
9
DQ
8
V
CAP
A
14
A
13
A
12
A
11
A
10
NC
NC
NC
2
3
4
5
6
A
0
A
1
A
2
A
3
A
4
E
DQ
0
DQ
1
DQ
2
DQ
3
V
CC
V
SS
DQ
4
DQ
5
DQ
6
DQ
7
W
A
5
A
6
A
7
A
8
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
LB
DQ
8
G
UB
A
0
A
3
A
5
A
17
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
A
2
E
NC
DQ
0
A
B
C
D
E
F
G
H
DQ
9
DQ
10
V
SS
DQ
11
DQ
1
DQ
2
DQ
3
DQ
4
V
CC
V
SS
(TOP)
(TOP)
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
CC
DQ
12
V
CAP
DQ
14
DQ
13
DQ
15
HSB
NC
A
8
A
14
A
12
A
9
DQ
5
DQ
6
W
A
11
DQ
7
NC
(TOP)
48-Ball FBGA
44-Pin TSOP-II
(See full mechanical drawings on pages 18 – 20)
54-Pin TSOP-II
PIN DESCRIPTIONS
Pin Name
A
17
-A
0
DQ
15
-DQ
0
E
LB
UB
W
G
V
CC
HSB
Input
I/O
Input
Input
Input
Input
Input
Power Supply
I/O
I/O
Description
Address: The 18 address inputs select one of 262,144 words in the nvSRAM array
Data: Bi-directional 16-bit data bus for accessing the nvSRAM
Chip Enable: The active low E input selects the device
Byte Write Select Input: Controls DQ7-DQ0 (unselected byte will not write or read).
Byte Write Select Input: Controls DQ15-DQ8 (unselected byte will not write or read).
Write Enable: The active low W enables data on the DQ pins to be written to the address location latched by the falling edge of E
Output Enable: The active low G input enables the data output buffers during read cycles. De-asserting G high causes the DQ pins
to tri-state.
Power: 3.0V +20%, -10%
Hardware Store Busy: When low this output indicates a Store is in progress (also low during power up while busy). When pulled
low external to the chip, it will initiate a nonvolatile STORE operation. A weak pull up resistor keeps this pin high if not connected.
(Connection Optional).
Autostore Capacitor: Supplies power to the nvSRAM during a power loss to store data from SRAM to nonvolatile storage ele-
ments.
Ground
This pin is not connected to the die. (Do not connect in design; reserved for future use)
V
CAP
V
SS
NC
Power Supply
Power Supply
No Connect
Document Control #ML0061 Rev 1.1
Jan, 2008
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Simtek Confidential
STK14EC16
ABSOLUTE MAXIMUM RATINGS
a
Voltage on Input Relative to Ground . . . . . . . . . . . . . –0.5V to 4.1V
Voltage on Input Relative to V
SS
. . . . . . . . . .–0.5V to (V
CC
+ 0.5V)
Voltage on DQ
0-7
or HSB . . . . . . . . . . . . . . . .–0.5V to (V
CC
+ 0.5V)
Temperature under Bias. . . . . . . . . . . . . . . . . . . . . .–55°C to 125°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .–55°C to 140°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .–65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration) . . . . . . . 15mA
Preliminary
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at con-
ditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
TF (TSOP-II 44) PACKAGE THERMAL CHARACTERISTICS
θ
jc
tbd;
θ
ja
tbd [0fpm], tbd [200fpm], tbd C/W [500fpm].
UF (TSOP-II 54) PACKAGE THERMAL CHARACTERISTICS
θ
jc
tbd;
θ
ja
tbd [0fpm], tbd [200fpm], tbd C/W [500fpm].
BF (FBGA48) PACKAGE THERMAL CHARACTERISTICS
θ
jc
tbd C/W;
θ
ja
tbd [0fpm], tbd [200fpm], tbd C/W [500fpm].
DC CHARACTERISTICS
COMMERCIAL
SYMBOL
I
CC1
PARAMETER
MIN
Average V
CC
Current
70
65
50
75
70
52
mA
mA
mA
MAX
MIN
MAX
INDUSTRIAL
UNITS
(V
CC
= 2.7V-3.6V)
NOTES
t
AVAV
= 15ns
t
AVAV
= 25ns
t
AVAV
= 45ns
Dependent on output loading and cycle
rate. Values obtained without output
loads.
All Inputs Don’t Care, V
CC
= max
Average current for duration of STORE
cycle (t
STORE
)
W
≥
(V
CC
– 0.2V)
All Other Inputs Cycling at CMOS Levels
Dependent on output loading and cycle
rate. Values obtained without output
loads.
All Inputs Don’t Care
Average current for duration of STORE
cycle (t
STORE
)
E
≥ (V
CC
-0.2V)
All Others V
IN
≤
0.2V or
≥
(V
CC
-0.2V)
Standby current level after nonvolatile
cycle complete
V
CC
= max
V
IN
= V
SS
to V
CC
V
CC
= max
V
IN
= V
SS
to V
CC
, E or G
≥
V
IH
All Inputs
All Inputs
I
OUT
= – 2mA (except HSB)
I
OUT
= 4mA
I
CC2
Average V
CC
Current during
STORE
6
6
mA
I
CC3
Average V
CC
Current at t
AVAV
= 200ns
3V, 25°C, Typical
26
26
mA
I
CC4
Average V
CAP
Current during Auto Store
Cycle
V
CC
Standby Current
(Standby, Stable CMOS Levels)
6
6
mA
I
SB
3
3
mA
I
ILK
I
OLK
V
IH
V
IL
V
OH
V
OL
T
A
V
CC
V
CAP
NV
C
DATA
R
Input Leakage Current
Off-State Output Leakage Current
Input Logic “1” Voltage
Input Logic “0” Voltage
Output Logic “1” Voltage
Output Logic “0” Voltage
Operating Temperature
Operating Voltage
Storage Capacitance
Nonvolatile STORE operations
Data Retention
0
2.7
61
200
20
2.0
V
SS
–0.5
2.4
±1
±1
V
CC
+ 0.5
0.8
2.0
V
SS
–0.5
2.4
0.4
70
3.6
134
– 40
2.7
61
200
20
±1
±1
V
CC
+ 0.5
0.8
μA
μA
V
V
V
0.4
85
3.6
180
V
°C
V
μF
K
Years
3.3V nominal
Between V
CAP
pin and V
SS
, 5V rated
(Nom. 68
μF
to 150
μF
+20%, - 10%)
@ 55 deg C
Note: The HSB pin has I
OUT
=-10 uA for V
OH
of 2.4 V. This parameter is characterized but not tested.
Document Control #ML0061 Rev 1.1
Jan, 2008
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Simtek Confidential
Preliminary
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input Rise and Fall Times
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤
5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1 and 2
STK14EC16
CAPACITANCE
b
SYMBOL
C
IN
C
OUT
PARAMETER
Input Capacitance
Output Capacitance
(T
A
= 25°C, f = 1.0MHz)
MAX
7
7
UNITS
pF
pF
CONDITIONS
ΔV
= 0 to 3V
ΔV
= 0 to 3V
Note b: These parameters are guaranteed but not tested.
3.0V
577 Ohms
OUTPUT
789 Ohms
30 pF
INCLUDING
SCOPE AND
FIXTURE
Figure 1
:
AC Output Loading
3.0V
577 Ohms
OUTPUT
789 Ohms
5 pF
INCLUDING
SCOPE AND
FIXTURE
Figure 2
:
AC Output Loading for Tristate Specs (t
HZ
, t
LZ
, t
WLQZ
, t
WHQZ
, t
GLQX
, t
GHQZ
)
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传感器
